Simulation Results: rom_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.12 %
  • code
  • 90.94 %
  • assert
  • 95.34 %
  • func
  • 93.08 %
  • line
  • 99.32 %
  • branch
  • 98.18 %
  • cond
  • 91.98 %
  • toggle
  • 98.55 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
33.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 3.970s 437.882us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.370s 172.480us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.360s 166.492us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.820s 559.045us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.580s 551.744us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.460s 177.424us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.360s 166.492us 1 1 100.00
rom_ctrl_csr_aliasing 3.580s 551.744us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.760s 2110.813us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.010s 1074.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.410s 400.701us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 9.390s 1166.772us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.450s 1135.953us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.210s 358.467us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 4.810s 300.809us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 4.810s 300.809us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 172.480us 1 1 100.00
rom_ctrl_csr_rw 4.360s 166.492us 1 1 100.00
rom_ctrl_csr_aliasing 3.580s 551.744us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 128.215us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.370s 172.480us 1 1 100.00
rom_ctrl_csr_rw 4.360s 166.492us 1 1 100.00
rom_ctrl_csr_aliasing 3.580s 551.744us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.660s 128.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.140s 850.438us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
rom_ctrl_tl_intg_err 22.990s 1027.486us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 3.970s 437.882us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 3.970s 437.882us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 3.970s 437.882us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.990s 1027.486us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
rom_ctrl_kmac_err_chk 7.450s 1135.953us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 23.430s 1443.856us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.140s 850.438us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 193.910s 530.951us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 157.590s 10118.422us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 84425417292234235228260960029508374539910171784944880480465941102162667370752 87
UVM_ERROR @ 1443856046 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
UVM_INFO @ 1443856046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 78373630346767063497210084859387222886871864043995581646105122010786531480507 236
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 10753702ps failed at 10753702ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 10753702ps failed at 10753702ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'