Simulation Results: rom_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.87 %
  • code
  • 95.84 %
  • assert
  • 95.34 %
  • func
  • 96.42 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 94.95 %
  • toggle
  • 99.59 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.890s 220.295us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.970s 1517.203us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.990s 906.086us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.580s 299.922us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.320s 3558.896us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.090s 713.589us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.990s 906.086us 1 1 100.00
rom_ctrl_csr_aliasing 7.320s 3558.896us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.040s 302.423us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.940s 209.555us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.690s 1355.922us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 24.040s 1614.412us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.300s 2105.058us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.010s 384.106us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.750s 383.690us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.750s 383.690us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.970s 1517.203us 1 1 100.00
rom_ctrl_csr_rw 5.990s 906.086us 1 1 100.00
rom_ctrl_csr_aliasing 7.320s 3558.896us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.210s 909.035us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.970s 1517.203us 1 1 100.00
rom_ctrl_csr_rw 5.990s 906.086us 1 1 100.00
rom_ctrl_csr_aliasing 7.320s 3558.896us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.210s 909.035us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.760s 4285.301us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
rom_ctrl_tl_intg_err 96.420s 1337.367us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.890s 220.295us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.890s 220.295us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.890s 220.295us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 96.420s 1337.367us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
rom_ctrl_kmac_err_chk 14.300s 2105.058us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 89.050s 5188.921us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 26.760s 4285.301us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 231.210s 532.232us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 240.600s 16500.342us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
rom_ctrl_sec_cm 20186109494657074876218919474878370765267543875346508431166199624553129790444 236
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 15258170ps failed at 15258170ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 15268271ps failed at 15268271ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'