Simulation Results: rstmgr

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.33 %
  • code
  • 99.36 %
  • assert
  • 97.44 %
  • func
  • 95.18 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.09 %
  • toggle
  • 99.43 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.060s 60.616us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.070s 92.508us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.430s 143.219us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 0.990s 38.580us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.030s 66.608us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00
rstmgr_csr_aliasing 0.990s 38.580us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.050s 96.703us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.900s 42.368us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.860s 62.131us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.290s 620.672us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.290s 620.672us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.290s 620.672us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.290s 620.672us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 13.520s 2054.236us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.860s 38.838us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.810s 46.445us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.810s 46.445us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 92.508us 1 1 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00
rstmgr_csr_aliasing 0.990s 38.580us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 42.243us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.070s 92.508us 1 1 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00
rstmgr_csr_aliasing 0.990s 38.580us 1 1 100.00
rstmgr_same_csr_outstanding 0.940s 42.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 30.160s 6803.797us 1 1 100.00
rstmgr_tl_intg_err 3.870s 619.849us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 30.160s 6803.797us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 30.160s 6803.797us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 3.870s 619.849us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.040s 67.386us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.450s 446.706us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.960s 291.382us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 30.160s 6803.797us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 38.719us 1 1 100.00

Error Messages

   Test seed line log context