Simulation Results: rv_timer

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.16 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 97.65 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.680s 102.484us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.600s 27.465us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.650s 38.667us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.260s 510.463us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.630s 32.219us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 18.831us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.650s 38.667us 1 1 100.00
rv_timer_csr_aliasing 0.630s 32.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.640s 125.631us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.200s 573.738us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 254.900s 230069.391us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 254.900s 230069.391us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.700s 228.830us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 44.863us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 169.569us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.020s 2995.393us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.020s 2995.393us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 27.465us 1 1 100.00
rv_timer_csr_rw 0.650s 38.667us 1 1 100.00
rv_timer_csr_aliasing 0.630s 32.219us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 23.369us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.600s 27.465us 1 1 100.00
rv_timer_csr_rw 0.650s 38.667us 1 1 100.00
rv_timer_csr_aliasing 0.630s 32.219us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 23.369us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.730s 798.082us 1 1 100.00
rv_timer_tl_intg_err 1.150s 137.787us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.150s 137.787us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.650s 145.632us 0 1 0.00
max_value 1 1 100.00
rv_timer_max 0.530s 10.091us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 26.500s 5147.013us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 4619500529083652411944148967128855892979968191184973051384012560898551378802 75
UVM_FATAL @ 145632025 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5180104) == 0x1
UVM_INFO @ 145632025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 26365189059748823384537036494152341131804089413810909462524207022878474259264 72
UVM_FATAL @ 125630842 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xecb75304) == 0x1
UVM_INFO @ 125630842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---