Simulation Results: sram_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.89 %
  • code
  • 93.80 %
  • assert
  • 95.69 %
  • func
  • 95.18 %
  • line
  • 98.48 %
  • branch
  • 96.78 %
  • cond
  • 92.53 %
  • toggle
  • 90.71 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.830s 2954.824us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.850s 39.292us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.650s 18.532us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.990s 464.408us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 74.979us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.530s 725.745us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.650s 18.532us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 74.979us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 103.250s 28167.783us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 123.050s 4921.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 652.730s 41683.247us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 151.930s 15934.241us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 571.020s 22588.377us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 498.670s 18691.125us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 47.050s 44606.108us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 934.280s 24679.492us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 50.200s 884.897us 1 1 100.00
sram_ctrl_partial_access_b2b 166.110s 49824.064us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 31.270s 3416.887us 1 1 100.00
sram_ctrl_throughput_w_partial_write 11.690s 2741.479us 1 1 100.00
sram_ctrl_throughput_w_readback 7.720s 2871.524us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 555.970s 14941.129us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.360s 1529.277us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 2918.980s 518376.889us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.930s 37.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.100s 167.681us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.100s 167.681us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.850s 39.292us 1 1 100.00
sram_ctrl_csr_rw 0.650s 18.532us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 74.979us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 36.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.850s 39.292us 1 1 100.00
sram_ctrl_csr_rw 0.650s 18.532us 1 1 100.00
sram_ctrl_csr_aliasing 0.880s 74.979us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.930s 36.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.760s 3802.442us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
sram_ctrl_tl_intg_err 2.180s 183.534us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.180s 183.534us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 555.970s 14941.129us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 555.970s 14941.129us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.650s 18.532us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 934.280s 24679.492us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 934.280s 24679.492us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 934.280s 24679.492us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 47.050s 44606.108us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.070s 702.633us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.760s 3802.442us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.790s 676.926us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.830s 2954.824us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.830s 2954.824us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 934.280s 24679.492us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 47.050s 44606.108us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.830s 2954.824us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.900s 1.721us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 80.590s 1798.710us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 39839672448951188355523094948214177609404325051839509741227681856142040392932 96
UVM_ERROR @ 1721223 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 1721223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---