Simulation Results: sram_ctrl

 
15/12/2025 16:03:12 sha: fc10746 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.02 %
  • code
  • 91.10 %
  • assert
  • 95.79 %
  • func
  • 95.18 %
  • line
  • 97.68 %
  • branch
  • 94.95 %
  • cond
  • 91.43 %
  • toggle
  • 90.47 %
  • FSM
  • 80.95 %
Validation stages
V1
90.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.060s 956.222us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.850s 72.561us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.700s 18.401us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.110s 29.670us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 50.801us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.460s 25.247us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.700s 18.401us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 50.801us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.840s 4011.817us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.200s 359.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 582.590s 83868.873us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 146.770s 2153.517us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 37.840s 3541.756us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 365.070s 7335.316us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.440s 1433.414us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 628.560s 15649.984us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 23.090s 324.484us 1 1 100.00
sram_ctrl_partial_access_b2b 191.070s 39870.246us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 41.560s 556.427us 1 1 100.00
sram_ctrl_throughput_w_partial_write 22.970s 600.830us 1 1 100.00
sram_ctrl_throughput_w_readback 58.360s 2105.526us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 156.140s 8343.325us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.950s 33.921us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1601.670s 33158.106us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.650s 32.614us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.790s 68.993us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.790s 68.993us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.850s 72.561us 1 1 100.00
sram_ctrl_csr_rw 0.700s 18.401us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 50.801us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 37.178us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.850s 72.561us 1 1 100.00
sram_ctrl_csr_rw 0.700s 18.401us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 50.801us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.690s 37.178us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.710s 968.719us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_tl_intg_err 1.220s 159.447us 1 1 100.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.220s 159.447us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 156.140s 8343.325us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 156.140s 8343.325us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.700s 18.401us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 628.560s 15649.984us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 628.560s 15649.984us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 628.560s 15649.984us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.440s 1433.414us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 0.850s 36.876us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 1.710s 968.719us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 1.160s 23.504us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.060s 956.222us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.060s 956.222us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 628.560s 15649.984us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.440s 1433.414us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.060s 956.222us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.720s 1.713us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 173.490s 6820.874us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: *
sram_ctrl_csr_mem_rw_with_rand_reset 60327172391751015215711007276198813625484341382513356356231518136820542909379 95
UVM_ERROR @ 25247313 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.init_done reset value: 0x0
UVM_INFO @ 25247313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3118) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }
sram_ctrl_readback_err 20285660618699783015343409513289797230085264458827868905822323484969427283783 95
UVM_ERROR @ 23504136 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3118) { a_addr: 'ha4c160f8 a_data: 'h16 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd5 a_opcode: 'h1 a_user: 'h26505 d_param: 'h0 d_source: 'hd5 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
UVM_INFO @ 23504136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(depth_o <= *'(Depth))'
sram_ctrl_sec_cm 28782068076805638971893062603077033580743641815142938324014142037605991172639 98
Offending '(depth_o <= 2'(Depth))'
UVM_ERROR @ 1712572 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
UVM_INFO @ 1712572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---