| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 1.410s | 558.986us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| uart_csr_hw_reset | 0.610s | 22.349us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 0.610s | 20.679us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 1.220s | 198.272us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| uart_csr_aliasing | 0.700s | 55.397us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 0.890s | 32.778us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| uart_csr_rw | 0.610s | 20.679us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.700s | 55.397us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 9.940s | 40234.660us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 1.410s | 558.986us | 1 | 1 | 100.00 | |
| uart_tx_rx | 9.940s | 40234.660us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 35.700s | 176019.168us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 15.950s | 107427.479us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 9.940s | 40234.660us | 1 | 1 | 100.00 | |
| uart_intr | 35.700s | 176019.168us | 1 | 1 | 100.00 | |
| fifo_full | 1 | 1 | 100.00 | |||
| uart_fifo_full | 15.220s | 41290.572us | 1 | 1 | 100.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 206.360s | 75644.336us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 16.080s | 163237.014us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 35.700s | 176019.168us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 35.700s | 176019.168us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 35.700s | 176019.168us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 97.560s | 13526.408us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 4.000s | 4836.498us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 4.000s | 4836.498us | 1 | 1 | 100.00 | |
| rx_noise_filter | 0 | 1 | 0.00 | |||
| uart_noise_filter | 1.190s | 5104.361us | 0 | 1 | 0.00 | |
| rx_start_bit_filter | 1 | 1 | 100.00 | |||
| uart_rx_start_bit_filter | 5.930s | 5146.369us | 1 | 1 | 100.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 1.900s | 5251.244us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 1.660s | 4579.666us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 355.670s | 138508.271us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| uart_stress_all | 1459.820s | 328025.852us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 0.560s | 39.771us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 0.630s | 27.214us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.510s | 91.523us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.510s | 91.523us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.610s | 22.349us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.610s | 20.679us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.700s | 55.397us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.670s | 38.644us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.610s | 22.349us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.610s | 20.679us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.700s | 55.397us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.670s | 38.644us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 0.930s | 174.579us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 1.010s | 68.935us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 1.010s | 68.935us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 10.390s | 6004.897us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * | ||||
| uart_noise_filter | 60214491639553185769991820133691655231160798569911324370305156363381958327033 | 71 |
UVM_ERROR @ 1220001019 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 8, clk_pulses: 0
UVM_ERROR @ 1220091928 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1220182837 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 207 [0xcf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 1220273746 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 1220364655 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 239 [0xef]) reg name: uart_reg_block.rdata
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