| V1 |
|
100.00% |
| V2 |
|
94.44% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_smoke | 1 | 1 | 100.00 | |||
| xbar_smoke | 11.370s | 554.190us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| xbar_base_random_sequence | 1 | 1 | 100.00 | |||
| xbar_random | 22.920s | 174.220us | 1 | 1 | 100.00 | |
| xbar_random_delay | 5 | 6 | 83.33 | |||
| xbar_smoke_zero_delays | 4.050s | 172.107us | 1 | 1 | 100.00 | |
| xbar_smoke_large_delays | 173.610s | 126402.994us | 1 | 1 | 100.00 | |
| xbar_smoke_slow_rsp | 211.230s | 39775.035us | 1 | 1 | 100.00 | |
| xbar_random_zero_delays | 3.840s | 21.184us | 1 | 1 | 100.00 | |
| xbar_random_large_delays | 104.470s | 22747.731us | 1 | 1 | 100.00 | |
| xbar_random_slow_rsp | 1401.880s | 600000.000us | 0 | 1 | 0.00 | |
| xbar_unmapped_address | 2 | 2 | 100.00 | |||
| xbar_unmapped_addr | 15.670s | 78.675us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 2.640s | 17.972us | 1 | 1 | 100.00 | |
| xbar_error_cases | 2 | 2 | 100.00 | |||
| xbar_error_random | 30.380s | 1608.201us | 1 | 1 | 100.00 | |
| xbar_error_and_unmapped_addr | 2.640s | 17.972us | 1 | 1 | 100.00 | |
| xbar_all_access_same_device | 2 | 2 | 100.00 | |||
| xbar_access_same_device | 18.720s | 149.023us | 1 | 1 | 100.00 | |
| xbar_access_same_device_slow_rsp | 2190.110s | 192873.257us | 1 | 1 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 1 | 1 | 100.00 | |||
| xbar_same_source | 25.000s | 636.730us | 1 | 1 | 100.00 | |
| xbar_stress_all | 2 | 2 | 100.00 | |||
| xbar_stress_all | 339.810s | 31164.791us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_error | 370.820s | 7650.784us | 1 | 1 | 100.00 | |
| xbar_stress_with_reset | 2 | 2 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 301.990s | 241.476us | 1 | 1 | 100.00 | |
| xbar_stress_all_with_reset_error | 49.890s | 22.666us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | ||||
| xbar_random_slow_rsp | 6002943048818485159784232063300613390419588489721464252727897685424611787926 | 177 |
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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