Simulation Results: ac_range_check

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.85 %
  • code
  • 93.07 %
  • assert
  • 97.63 %
  • func
  • 57.84 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 80.91 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 663.611us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 42.000s 2322.399us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 67.976us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 21.404us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 1713.572us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 20.000s 4303.508us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 93.163us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 21.404us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 4303.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 3.000s 57.525us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 27.000s 561.606us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 78.000s 4280.361us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 63.632us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 1.000s 47.989us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 64.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 64.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 67.976us 1 1 100.00
ac_range_check_csr_rw 3.000s 21.404us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 4303.508us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 172.788us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 2.000s 67.976us 1 1 100.00
ac_range_check_csr_rw 3.000s 21.404us 1 1 100.00
ac_range_check_csr_aliasing 20.000s 4303.508us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 172.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 822.433us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 822.433us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 822.433us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 14.000s 822.433us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 84.000s 7535.326us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 2.000s 11.742us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 743.863us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 233.000s 1595.535us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 19.000s 1674.370us 1 1 100.00

Error Messages

   Test seed line log context