| V1 |
|
100.00% |
| V2 |
|
95.83% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.010s | 142.911us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_csr_rw | 7.760s | 1243.415us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 175.160s | 10879.337us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 59.520s | 952.878us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 9.530s | 1141.914us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| alert_handler_csr_rw | 7.760s | 1243.415us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 59.520s | 952.878us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 1 | 1 | 100.00 | |||
| alert_handler_esc_alert_accum | 114.610s | 1799.806us | 1 | 1 | 100.00 | |
| esc_timeout | 1 | 1 | 100.00 | |||
| alert_handler_esc_intr_timeout | 18.830s | 247.923us | 1 | 1 | 100.00 | |
| entropy | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 1329.840s | 53817.379us | 1 | 1 | 100.00 | |
| sig_int_fail | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 46.500s | 2114.911us | 1 | 1 | 100.00 | |
| clk_skew | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| random_alerts | 1 | 1 | 100.00 | |||
| alert_handler_random_alerts | 35.760s | 4812.579us | 1 | 1 | 100.00 | |
| random_classes | 1 | 1 | 100.00 | |||
| alert_handler_random_classes | 26.550s | 546.679us | 1 | 1 | 100.00 | |
| ping_timeout | 0 | 1 | 0.00 | |||
| alert_handler_ping_timeout | 11.490s | 1559.791us | 0 | 1 | 0.00 | |
| lpg | 2 | 2 | 100.00 | |||
| alert_handler_lpg | 2131.300s | 634629.675us | 1 | 1 | 100.00 | |
| alert_handler_lpg_stub_clk | 1552.700s | 267611.912us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| alert_handler_stress_all | 2064.880s | 423748.169us | 1 | 1 | 100.00 | |
| alert_handler_entropy_stress_test | 1 | 1 | 100.00 | |||
| alert_handler_entropy_stress | 26.940s | 3492.316us | 1 | 1 | 100.00 | |
| alert_handler_alert_accum_saturation | 1 | 1 | 100.00 | |||
| alert_handler_alert_accum_saturation | 2.710s | 61.508us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| alert_handler_intr_test | 1.770s | 11.783us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 15.530s | 1132.632us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| alert_handler_tl_errors | 15.530s | 1132.632us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.010s | 142.911us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.760s | 1243.415us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 59.520s | 952.878us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 10.810s | 441.066us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| alert_handler_csr_hw_reset | 8.010s | 142.911us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 7.760s | 1243.415us | 1 | 1 | 100.00 | |
| alert_handler_csr_aliasing | 59.520s | 952.878us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 10.810s | 441.066us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 199.420s | 7832.516us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 199.420s | 7832.516us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 199.420s | 7832.516us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 199.420s | 7832.516us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 451.880s | 8922.376us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| alert_handler_tl_intg_err | 16.290s | 348.793us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| alert_handler_tl_intg_err | 16.290s | 348.793us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| alert_handler_shadow_reg_errors | 199.420s | 7832.516us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| sec_cm_alert_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| sec_cm_class_config_regwen | 1 | 1 | 100.00 | |||
| alert_handler_smoke | 50.380s | 2617.794us | 1 | 1 | 100.00 | |
| sec_cm_alert_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 46.500s | 2114.911us | 1 | 1 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 1 | 1 | 100.00 | |||
| alert_handler_lpg | 2131.300s | 634629.675us | 1 | 1 | 100.00 | |
| sec_cm_esc_intersig_diff | 1 | 1 | 100.00 | |||
| alert_handler_sig_int_fail | 46.500s | 2114.911us | 1 | 1 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 1329.840s | 53817.379us | 1 | 1 | 100.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 1 | 1 | 100.00 | |||
| alert_handler_entropy | 1329.840s | 53817.379us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_accu_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 1 | 1 | 100.00 | |||
| alert_handler_sec_cm | 8.670s | 178.905us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| alert_handler_stress_all_with_rand_reset | 192.330s | 16632.752us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (* [*] vs * [*]) | ||||
| alert_handler_ping_timeout | 86526929543031576387943940056296849337497837006286444207289510047669416143838 | 78 |
UVM_ERROR @ 1559790851 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1559790851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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