Simulation Results: clkmgr

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.56 %
  • code
  • 79.15 %
  • assert
  • 92.36 %
  • func
  • 73.17 %
  • line
  • 91.43 %
  • branch
  • 94.01 %
  • cond
  • 86.05 %
  • toggle
  • 99.25 %
  • FSM
  • 25.00 %
Validation stages
V1
50.00%
V2
63.16%
V2S
76.47%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.020s 33.618us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.940s 32.474us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.640s 2.182us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.100s 54.697us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.720s 2.721us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
clkmgr_csr_aliasing 1.100s 54.697us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.900s 43.697us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.180s 39.458us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.830s 24.576us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.020s 33.618us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.660s 5.251us 0 1 0.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 0.850s 14.862us 1 1 100.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.660s 5.251us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.730s 14.114us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.030s 52.836us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.720s 60.231us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.720s 60.231us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.940s 32.474us 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
clkmgr_csr_aliasing 1.100s 54.697us 0 1 0.00
clkmgr_same_csr_outstanding 0.780s 12.331us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.940s 32.474us 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
clkmgr_csr_aliasing 1.100s 54.697us 0 1 0.00
clkmgr_same_csr_outstanding 0.780s 12.331us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 8.830s 1006.205us 1 1 100.00
clkmgr_tl_intg_err 0.870s 14.074us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.070s 44.052us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.070s 44.052us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.070s 44.052us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.070s 44.052us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.670s 6.473us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.870s 14.074us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.660s 5.251us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 0.850s 14.862us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.070s 44.052us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.860s 23.386us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 8.830s 1006.205us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 15.358us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 8.830s 1006.205us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.640s 3.285us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 1.490s 71.937us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 84635712254496295315935164287308797293489643808763974138529756055473990023990 73
UVM_ERROR @ 5250974 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 5250974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 67097659958608091396567892793230965677420983824647166413406181690441686560808 75
UVM_ERROR @ 71937470 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 71937470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 44502136846456752674773667705320704160023693074331133971680752143468017486282 72
UVM_ERROR @ 14113535 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b01, got 0b00
UVM_INFO @ 14113535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en
clkmgr_regwen 18238114556302228496517872829175206526713950587146463809337558472911893888809 71
UVM_ERROR @ 3284994 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (15 [0xf] vs 9 [0x9]) reg name: clkmgr_reg_block.main_meas_ctrl_en
UVM_INFO @ 3284994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 88096663891305576906784106277660483379717156525521951847976908451303515452575 72
UVM_ERROR @ 6472758 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 6472758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 50633790458710142958171355921921392540294622045966175968354092398668407389047 79
UVM_ERROR @ 14073901 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 14073901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 57829847086084022515338021778761350840936711869984303127959909009778972264636 72
UVM_ERROR @ 2181957 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 2181957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_csr_aliasing 45755332525896502031751489465539332077912990031624528744956065895408848770699 73
UVM_ERROR @ 54697313 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 54697313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 112240430946489328220676198147551319254505480006411332842717835771797277646908 73
UVM_ERROR @ 2720662 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 2720662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 108903597514487716684070473109898984264944831560940777510345659639464605635611 72
UVM_ERROR @ 12330516 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x20e1d1e4 read out mismatch
UVM_INFO @ 12330516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---