Simulation Results: csrng

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.65 %
  • code
  • 92.27 %
  • assert
  • 92.79 %
  • func
  • 80.89 %
  • block
  • 96.95 %
  • line
  • 97.73 %
  • branch
  • 92.32 %
  • toggle
  • 93.31 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 22.521us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 23.120us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 36.034us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 523.129us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 7.000s 406.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 33.409us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 36.034us 1 1 100.00
csrng_csr_aliasing 7.000s 406.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 175.693us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 90.000s 8203.397us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 90.000s 8203.397us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 355.000s 9243.982us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 140.987us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 49.640us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 4.000s 66.833us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 4.000s 66.833us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 23.120us 1 1 100.00
csrng_csr_rw 2.000s 36.034us 1 1 100.00
csrng_csr_aliasing 7.000s 406.324us 1 1 100.00
csrng_same_csr_outstanding 4.000s 57.336us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 23.120us 1 1 100.00
csrng_csr_rw 2.000s 36.034us 1 1 100.00
csrng_csr_aliasing 7.000s 406.324us 1 1 100.00
csrng_same_csr_outstanding 4.000s 57.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 16.000s 510.026us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 36.034us 1 1 100.00
csrng_regwen 3.000s 33.657us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 175.693us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 355.000s 9243.982us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 175.693us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 355.000s 9243.982us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 175.693us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 16.000s 510.026us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
csrng_sec_cm 3.000s 152.901us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 75.078us 1 1 100.00
csrng_err 2.000s 36.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 103.000s 3186.086us 1 1 100.00

Error Messages

   Test seed line log context