Simulation Results: dma

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.70 %
  • code
  • 91.82 %
  • assert
  • 95.87 %
  • func
  • 60.40 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 315.490us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 230.184us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 1100.075us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 37.148us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 41.808us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 1530.214us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 5.000s 600.708us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 25.497us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 41.808us 1 1 100.00
dma_csr_aliasing 5.000s 600.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 22.000s 1509.737us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 126.000s 12209.934us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 328.000s 32381.068us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 328.000s 32381.068us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 126.000s 12209.934us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 512.000s 579621.070us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 328.000s 32381.068us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 1270.331us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 71.000s 6452.846us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 48.016us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 16.636us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 129.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 129.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 37.148us 1 1 100.00
dma_csr_rw 2.000s 41.808us 1 1 100.00
dma_csr_aliasing 5.000s 600.708us 1 1 100.00
dma_same_csr_outstanding 2.000s 496.060us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 37.148us 1 1 100.00
dma_csr_rw 2.000s 41.808us 1 1 100.00
dma_csr_aliasing 5.000s 600.708us 1 1 100.00
dma_same_csr_outstanding 2.000s 496.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 85.373us 1 1 100.00
dma_generic_stress 512.000s 579621.070us 1 1 100.00
dma_handshake_stress 328.000s 32381.068us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1445.322us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 96.980us 1 1 100.00
dma_sec_cm 1.000s 33.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 60.000s 14562.306us 1 1 100.00
dma_longer_transfer 5.000s 1100.202us 1 1 100.00
dma_stress_all_with_rand_reset 3.000s 465.246us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 102254647732056708147061909379130946298422383513110598408180778543197292377384 88
UVM_ERROR @ 465246040ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 465246040ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---