Simulation Results: edn

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.19 %
  • code
  • 83.24 %
  • assert
  • 96.96 %
  • func
  • 78.37 %
  • line
  • 97.93 %
  • branch
  • 93.31 %
  • cond
  • 87.70 %
  • toggle
  • 85.64 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.010s 61.090us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.030s 16.373us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 184.390us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.670s 37.573us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.320s 37.864us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.700s 46.210us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 184.390us 1 1 100.00
edn_csr_aliasing 1.320s 37.864us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.220s 38.861us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.220s 38.861us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.220s 38.861us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.010s 22.220us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 46.720us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 37.535us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 81.049us 1 1 100.00
edn_disable_auto_req_mode 1.050s 100.342us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.500s 256.019us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 146.005us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 50.919us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.370s 399.292us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.370s 399.292us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.030s 16.373us 1 1 100.00
edn_csr_rw 1.000s 184.390us 1 1 100.00
edn_csr_aliasing 1.320s 37.864us 1 1 100.00
edn_same_csr_outstanding 1.100s 56.308us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.030s 16.373us 1 1 100.00
edn_csr_rw 1.000s 184.390us 1 1 100.00
edn_csr_aliasing 1.320s 37.864us 1 1 100.00
edn_same_csr_outstanding 1.100s 56.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
edn_tl_intg_err 2.310s 81.966us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.890s 39.784us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 46.720us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 46.720us 1 1 100.00
edn_sec_cm 3.780s 256.825us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 46.720us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.310s 81.966us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 7.780s 359.705us 1 1 100.00

Error Messages

   Test seed line log context