Simulation Results: edn

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.67 %
  • code
  • 83.47 %
  • assert
  • 97.14 %
  • func
  • 79.41 %
  • line
  • 97.80 %
  • branch
  • 92.86 %
  • cond
  • 91.23 %
  • toggle
  • 95.70 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 25.611us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.810s 44.844us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 26.333us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.970s 1192.910us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.970s 48.675us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.180s 35.475us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 26.333us 1 1 100.00
edn_csr_aliasing 0.970s 48.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.110s 47.237us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.110s 47.237us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.110s 47.237us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.050s 31.352us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.140s 117.925us 1 1 100.00
errs 1 1 100.00
edn_err 1.040s 21.726us 1 1 100.00
disable 2 2 100.00
edn_disable 0.730s 22.164us 1 1 100.00
edn_disable_auto_req_mode 0.960s 62.736us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.310s 152.484us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.940s 43.195us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.840s 37.849us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 3.050s 1027.663us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 3.050s 1027.663us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.810s 44.844us 1 1 100.00
edn_csr_rw 0.750s 26.333us 1 1 100.00
edn_csr_aliasing 0.970s 48.675us 1 1 100.00
edn_same_csr_outstanding 1.130s 183.777us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.810s 44.844us 1 1 100.00
edn_csr_rw 0.750s 26.333us 1 1 100.00
edn_csr_aliasing 0.970s 48.675us 1 1 100.00
edn_same_csr_outstanding 1.130s 183.777us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
edn_tl_intg_err 1.710s 63.609us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.910s 63.494us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.140s 117.925us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.140s 117.925us 1 1 100.00
edn_sec_cm 6.030s 523.056us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.140s 117.925us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.710s 63.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 106.400s 99039.083us 1 1 100.00

Error Messages

   Test seed line log context