Simulation Results: hmac

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.57 %
  • code
  • 98.01 %
  • assert
  • 96.42 %
  • func
  • 44.28 %
  • line
  • 99.79 %
  • branch
  • 99.67 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 7.910s 441.215us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.880s 21.587us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.710s 16.615us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.410s 602.784us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.740s 212.681us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.380s 126.141us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.710s 16.615us 1 1 100.00
hmac_csr_aliasing 2.740s 212.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 52.260s 1563.267us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 33.910s 8860.603us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.110s 3607.151us 1 1 100.00
hmac_test_sha384_vectors 19.910s 206.605us 1 1 100.00
hmac_test_sha512_vectors 403.640s 13330.332us 1 1 100.00
hmac_test_hmac256_vectors 7.080s 2314.319us 1 1 100.00
hmac_test_hmac384_vectors 10.360s 505.399us 1 1 100.00
hmac_test_hmac512_vectors 11.540s 261.370us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 8.750s 1647.189us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 360.120s 11518.623us 1 1 100.00
error 1 1 100.00
hmac_error 36.660s 4424.080us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 69.940s 7918.978us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 7.910s 441.215us 1 1 100.00
hmac_long_msg 52.260s 1563.267us 1 1 100.00
hmac_back_pressure 33.910s 8860.603us 1 1 100.00
hmac_datapath_stress 360.120s 11518.623us 1 1 100.00
hmac_burst_wr 8.750s 1647.189us 1 1 100.00
hmac_stress_all 97.920s 7300.723us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 7.910s 441.215us 1 1 100.00
hmac_long_msg 52.260s 1563.267us 1 1 100.00
hmac_back_pressure 33.910s 8860.603us 1 1 100.00
hmac_datapath_stress 360.120s 11518.623us 1 1 100.00
hmac_wipe_secret 69.940s 7918.978us 1 1 100.00
hmac_test_sha256_vectors 9.110s 3607.151us 1 1 100.00
hmac_test_sha384_vectors 19.910s 206.605us 1 1 100.00
hmac_test_sha512_vectors 403.640s 13330.332us 1 1 100.00
hmac_test_hmac256_vectors 7.080s 2314.319us 1 1 100.00
hmac_test_hmac384_vectors 10.360s 505.399us 1 1 100.00
hmac_test_hmac512_vectors 11.540s 261.370us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 7.910s 441.215us 1 1 100.00
hmac_long_msg 52.260s 1563.267us 1 1 100.00
hmac_back_pressure 33.910s 8860.603us 1 1 100.00
hmac_datapath_stress 360.120s 11518.623us 1 1 100.00
hmac_burst_wr 8.750s 1647.189us 1 1 100.00
hmac_error 36.660s 4424.080us 1 1 100.00
hmac_wipe_secret 69.940s 7918.978us 1 1 100.00
hmac_test_sha256_vectors 9.110s 3607.151us 1 1 100.00
hmac_test_sha384_vectors 19.910s 206.605us 1 1 100.00
hmac_test_sha512_vectors 403.640s 13330.332us 1 1 100.00
hmac_test_hmac256_vectors 7.080s 2314.319us 1 1 100.00
hmac_test_hmac384_vectors 10.360s 505.399us 1 1 100.00
hmac_test_hmac512_vectors 11.540s 261.370us 1 1 100.00
hmac_stress_all 97.920s 7300.723us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 97.920s 7300.723us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.850s 49.907us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 159.223us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.030s 48.793us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.030s 48.793us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.880s 21.587us 1 1 100.00
hmac_csr_rw 0.710s 16.615us 1 1 100.00
hmac_csr_aliasing 2.740s 212.681us 1 1 100.00
hmac_same_csr_outstanding 2.710s 818.939us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.880s 21.587us 1 1 100.00
hmac_csr_rw 0.710s 16.615us 1 1 100.00
hmac_csr_aliasing 2.740s 212.681us 1 1 100.00
hmac_same_csr_outstanding 2.710s 818.939us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.340s 674.353us 1 1 100.00
hmac_tl_intg_err 1.840s 57.793us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.840s 57.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 7.910s 441.215us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.280s 139.063us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 221.220s 8159.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.210s 588.195us 1 1 100.00

Error Messages

   Test seed line log context