Simulation Results: i2c

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.04 %
  • code
  • 81.05 %
  • assert
  • 95.98 %
  • func
  • 81.08 %
  • line
  • 96.35 %
  • branch
  • 92.12 %
  • cond
  • 84.48 %
  • toggle
  • 89.45 %
  • FSM
  • 42.86 %
Validation stages
V1
100.00%
V2
87.76%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 18.810s 7947.677us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 14.850s 771.406us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.740s 23.165us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.700s 24.319us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 1.820s 65.228us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.330s 41.997us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.940s 87.748us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.700s 24.319us 1 1 100.00
i2c_csr_aliasing 1.330s 41.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 1.580s 220.976us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 75.690s 21663.279us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 19.510s 748.163us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.640s 39.158us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 91.030s 4961.332us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 25.560s 1395.894us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.890s 442.356us 1 1 100.00
i2c_host_fifo_fmt_empty 5.070s 944.029us 1 1 100.00
i2c_host_fifo_reset_rx 2.020s 574.593us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 55.390s 4432.339us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 8.210s 2463.811us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.750s 26.839us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.830s 516.944us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 108.440s 26902.913us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.510s 2937.429us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 16.490s 2579.565us 1 1 100.00
i2c_target_intr_smoke 4.310s 2119.036us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.070s 188.260us 1 1 100.00
i2c_target_fifo_reset_tx 0.860s 211.178us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 19.630s 30239.463us 1 1 100.00
i2c_target_stress_rd 16.490s 2579.565us 1 1 100.00
i2c_target_intr_stress_wr 16.520s 3555.176us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.050s 1047.321us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 21.660s 2929.843us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.980s 14448.390us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 17.280s 10013.460us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.700s 552.422us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.880s 456.499us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 19.510s 748.163us 1 1 100.00
i2c_host_perf_precise 60.210s 2384.603us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 8.210s 2463.811us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.350s 74.290us 1 1 100.00
target_mode_nack_generation 2 3 66.67
i2c_target_nack_acqfull 1.860s 881.462us 1 1 100.00
i2c_target_nack_acqfull_addr 1.780s 888.190us 1 1 100.00
i2c_target_nack_txstretch 1.060s 144.480us 0 1 0.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 15.540s 593.010us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.600s 1838.237us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.590s 15.059us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.630s 24.432us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 0.840s 36.887us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 0.840s 36.887us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.740s 23.165us 1 1 100.00
i2c_csr_rw 0.700s 24.319us 1 1 100.00
i2c_csr_aliasing 1.330s 41.997us 1 1 100.00
i2c_same_csr_outstanding 0.780s 33.186us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.740s 23.165us 1 1 100.00
i2c_csr_rw 0.700s 24.319us 1 1 100.00
i2c_csr_aliasing 1.330s 41.997us 1 1 100.00
i2c_same_csr_outstanding 0.780s 33.186us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.830s 73.026us 1 1 100.00
i2c_tl_intg_err 1.700s 137.226us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.700s 137.226us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 1.890s 424.462us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.880s 67.960us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 3.340s 470.258us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 90660627004180223399242194117920936232867498371917837725376686946446185614084 99
UVM_ERROR @ 220976422 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 220976422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 33916133309436234017967569487713101842880366315332062616180780413921840897958 125
UVM_ERROR @ 21663279137 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 21663279137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 26489492895697313258234809954176596577446150360762809849330604747865273858158 85
UVM_ERROR @ 470257731 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 470257731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 74226053915759568571569202698702141338942536213245219727127322664720004330939 81
UVM_ERROR @ 516944178 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 516944178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 58571939889669189430354248551296695287060638623484265338303202000292618320761 75
UVM_ERROR @ 67959719 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 67959719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 39974109599863057806614155759799760773208405740474931701226540442232178094261 76
UVM_FATAL @ 10013460111 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10013460111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 83870711396232755827526670965389301468881720769190458299182427172224899201894 81
UVM_ERROR @ 424461544 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 424461544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
i2c_host_mode_toggle 79549858770912061857744600097529792418586954249189111649160082798589728940701 84
UVM_ERROR @ 26839413 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: *
i2c_target_nack_txstretch 21172516497224432743877873657702997298530619769370075616809058116717635947813 75
UVM_ERROR @ 144480479 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 144480479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---