| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_dpe_smoke | 23.740s | 1989.163us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.180s | 35.570us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_rw | 0.800s | 26.223us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_bit_bash | 7.850s | 3677.217us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_aliasing | 4.430s | 157.553us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_dpe_csr_mem_rw_with_rand_reset | 2.170s | 170.498us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_dpe_csr_rw | 0.800s | 26.223us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.430s | 157.553us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_intr_test | 0.970s | 42.327us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_dpe_alert_test | 0.700s | 38.849us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.300s | 78.525us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_dpe_tl_errors | 2.300s | 78.525us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.180s | 35.570us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 0.800s | 26.223us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.430s | 157.553us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 1.260s | 102.522us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_dpe_csr_hw_reset | 1.180s | 35.570us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_rw | 0.800s | 26.223us | 1 | 1 | 100.00 | |
| keymgr_dpe_csr_aliasing | 4.430s | 157.553us | 1 | 1 | 100.00 | |
| keymgr_dpe_same_csr_outstanding | 1.260s | 102.522us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_dpe_tl_intg_err | 2.220s | 192.775us | 1 | 1 | 100.00 | |
| keymgr_dpe_sec_cm | 10.190s | 1750.022us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.360s | 110.497us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.360s | 110.497us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.360s | 110.497us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors | 1.360s | 110.497us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_dpe_shadow_reg_errors_with_csr_rw | 3.200s | 403.701us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 10.190s | 1750.022us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_dpe_sec_cm | 10.190s | 1750.022us | 1 | 1 | 100.00 | |
| Test | seed | line | log context |
|---|