Simulation Results: lc_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.45 %
  • code
  • 89.87 %
  • assert
  • 95.99 %
  • func
  • 88.49 %
  • line
  • 97.74 %
  • branch
  • 96.34 %
  • cond
  • 79.84 %
  • toggle
  • 82.57 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.190s 118.146us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.920s 18.552us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.576us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.350s 39.562us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 93.649us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.810s 18.270us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 18.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 93.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.490s 202.446us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.610s 395.225us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 23.482us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.160s 19.398us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.250s 2407.031us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_prog_failure 1.160s 19.398us 1 1 100.00
lc_ctrl_errors 5.250s 2407.031us 1 1 100.00
lc_ctrl_security_escalation 7.020s 351.053us 1 1 100.00
lc_ctrl_jtag_state_failure 3.320s 527.408us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.700s 2316.826us 1 1 100.00
lc_ctrl_jtag_errors 25.030s 6481.848us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 2.240s 107.130us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.870s 165.058us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.490s 394.195us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.460s 243.252us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.240s 28.494us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.800s 221.864us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 42.511us 1 1 100.00
lc_ctrl_jtag_smoke 3.530s 725.255us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.350s 125.651us 0 1 0.00
lc_ctrl_jtag_prog_failure 6.700s 2316.826us 1 1 100.00
lc_ctrl_jtag_errors 25.030s 6481.848us 1 1 100.00
lc_ctrl_jtag_access 1.160s 57.876us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.220s 1673.740us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.330s 842.409us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.760s 44.725us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10.320s 2096.435us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 21.925us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.230s 41.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.230s 41.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 18.552us 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 93.649us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 24.320us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.920s 18.552us 1 1 100.00
lc_ctrl_csr_rw 0.920s 18.576us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 93.649us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.900s 24.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.300s 250.204us 1 1 100.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.300s 250.204us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.610s 395.225us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.830s 10.803us 0 1 0.00
lc_ctrl_sec_cm 6.610s 505.663us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.020s 351.053us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 2.490s 202.446us 1 1 100.00
lc_ctrl_jtag_state_post_trans 1.350s 125.651us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.920s 3892.377us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.920s 3892.377us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.970s 716.353us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.250s 310.020us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.250s 310.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.190s 7.772us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 61496789962020392942020836348942787921078265819328683500433228134096912040380 254
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 10803094 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 10803094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 60544826955688986517105340936596048007756324416057254909253991431194391859398 506
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 527408252 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 527408252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 84057649590323316490021782362494582319675126894361338177963536703596938653713 191
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 125650501 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 125650501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 107683904962909574216422077422939724749736838388652162619147221588666350085433 985
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2096434786 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2096434786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 70131705877846918168056201434348670020121872113150627119392589712254303669637 193
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 7771643 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 7771643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---