Simulation Results: lc_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.36 %
  • code
  • 86.42 %
  • assert
  • 95.99 %
  • func
  • 88.67 %
  • line
  • 97.45 %
  • branch
  • 95.38 %
  • cond
  • 79.07 %
  • toggle
  • 76.50 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
87.50%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.050s 47.724us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 23.782us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 14.127us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.300s 130.292us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 16.996us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.020s 23.286us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 14.127us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 16.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.120s 278.783us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 11.600s 321.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 23.788us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.480s 237.480us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.520s 1233.683us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_prog_failure 1.480s 237.480us 1 1 100.00
lc_ctrl_errors 4.520s 1233.683us 1 1 100.00
lc_ctrl_security_escalation 8.670s 1311.050us 1 1 100.00
lc_ctrl_jtag_state_failure 26.800s 5076.951us 0 1 0.00
lc_ctrl_jtag_prog_failure 9.230s 911.726us 1 1 100.00
lc_ctrl_jtag_errors 12.310s 1298.839us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.090s 117.928us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.050s 122.741us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.130s 1430.390us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.500s 1393.971us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.220s 119.216us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.470s 161.857us 1 1 100.00
lc_ctrl_jtag_alert_test 1.030s 101.450us 1 1 100.00
lc_ctrl_jtag_smoke 7.630s 871.913us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.040s 125.059us 0 1 0.00
lc_ctrl_jtag_prog_failure 9.230s 911.726us 1 1 100.00
lc_ctrl_jtag_errors 12.310s 1298.839us 1 1 100.00
lc_ctrl_jtag_access 7.040s 1696.525us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 25.440s 1310.666us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.920s 740.147us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 15.926us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 9.770s 559.657us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.840s 21.679us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 28.430us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.350s 28.430us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 23.782us 1 1 100.00
lc_ctrl_csr_rw 0.730s 14.127us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 16.996us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.840s 15.837us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 23.782us 1 1 100.00
lc_ctrl_csr_rw 0.730s 14.127us 1 1 100.00
lc_ctrl_csr_aliasing 0.910s 16.996us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.840s 15.837us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.750s 257.393us 1 1 100.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.750s 257.393us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 11.600s 321.000us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 2.990s 46.485us 0 1 0.00
lc_ctrl_sec_cm 6.510s 233.874us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.670s 1311.050us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 1 2 50.00
lc_ctrl_state_post_trans 5.120s 278.783us 1 1 100.00
lc_ctrl_jtag_state_post_trans 4.040s 125.059us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.870s 1463.767us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.870s 1463.767us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.160s 921.443us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.650s 277.685us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.650s 277.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3.850s 298.212us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 46042126515494284233815583600424803283428373251358996035346414565069797713299 303
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 46484538 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 46484538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 22314992723899213190261332072097192196056647916670171213311916524540370591908 2261
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 5076950691 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 5076950691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 70377659799996796113403016574405679456107176034957696734754376130007674230393 323
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 125058948 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 125058948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 29723011742181376041265183757285101842746537894843881780928202224985392836202 814
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 559656804 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 559656804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3361324502923062260441551777680914734209886676798240458438473151351699265258 240
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 298211520 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 298211520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---