| V1 |
|
100.00% |
| V2 |
|
93.75% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 68.000s | 4882.307us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 24.401us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 1.000s | 46.962us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 4.000s | 701.532us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 85.781us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 95.846us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 1.000s | 46.962us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 85.781us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 0 | 1 | 0.00 | |||
| mbx_stress | 17.000s | 625.767us | 0 | 1 | 0.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 82.000s | 6706.449us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 19.000s | 5597.774us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 12.000s | 1370.236us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 1.000s | 19.808us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 1.000s | 61.094us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 4.000s | 64.008us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 4.000s | 64.008us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 24.401us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 46.962us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 85.781us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 51.839us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 2.000s | 24.401us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 1.000s | 46.962us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 85.781us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 1.000s | 51.839us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 2.000s | 28.795us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 2.000s | 1042.775us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register | ||||
| mbx_stress | 62306813339625902027038450508722782992418008930889073474118239127778459378260 | 216 |
UVM_ERROR @ 625767072 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 625767072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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