| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
75.81% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 136.967us | 1 | 1 | 100.00 | |
| single_binary | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 23.706us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| otbn_csr_rw | 3.000s | 23.142us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| otbn_csr_bit_bash | 5.000s | 25.083us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| otbn_csr_aliasing | 4.000s | 56.071us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_csr_mem_rw_with_rand_reset | 5.000s | 100.602us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| otbn_csr_rw | 3.000s | 23.142us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 56.071us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| otbn_mem_walk | 18.000s | 3501.467us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| otbn_mem_partial_access | 17.000s | 1770.095us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reset_recovery | 1 | 1 | 100.00 | |||
| otbn_reset | 23.000s | 276.148us | 1 | 1 | 100.00 | |
| multi_error | 1 | 1 | 100.00 | |||
| otbn_multi_err | 48.000s | 441.655us | 1 | 1 | 100.00 | |
| back_to_back | 1 | 1 | 100.00 | |||
| otbn_multi | 28.000s | 383.974us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| otbn_stress_all | 19.000s | 74.679us | 1 | 1 | 100.00 | |
| lc_escalation | 1 | 1 | 100.00 | |||
| otbn_escalate | 9.000s | 21.494us | 1 | 1 | 100.00 | |
| zero_state_err_urnd | 1 | 1 | 100.00 | |||
| otbn_zero_state_err_urnd | 6.000s | 31.975us | 1 | 1 | 100.00 | |
| sw_errs_fatal_chk | 1 | 1 | 100.00 | |||
| otbn_sw_errs_fatal_chk | 5.000s | 22.605us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| otbn_alert_test | 4.000s | 52.735us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| otbn_intr_test | 4.000s | 18.037us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 93.411us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| otbn_tl_errors | 4.000s | 93.411us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 23.706us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 23.142us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 56.071us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 36.254us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| otbn_csr_hw_reset | 3.000s | 23.706us | 1 | 1 | 100.00 | |
| otbn_csr_rw | 3.000s | 23.142us | 1 | 1 | 100.00 | |
| otbn_csr_aliasing | 4.000s | 56.071us | 1 | 1 | 100.00 | |
| otbn_same_csr_outstanding | 4.000s | 36.254us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mem_integrity | 2 | 2 | 100.00 | |||
| otbn_imem_err | 9.000s | 97.396us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 67.320us | 1 | 1 | 100.00 | |
| internal_integrity | 4 | 4 | 100.00 | |||
| otbn_alu_bignum_mod_err | 6.000s | 107.634us | 1 | 1 | 100.00 | |
| otbn_controller_ispr_rdata_err | 8.000s | 276.977us | 1 | 1 | 100.00 | |
| otbn_mac_bignum_acc_err | 37.000s | 609.882us | 1 | 1 | 100.00 | |
| otbn_urnd_err | 4.000s | 45.174us | 1 | 1 | 100.00 | |
| illegal_bus_access | 1 | 1 | 100.00 | |||
| otbn_illegal_mem_acc | 5.000s | 14.274us | 1 | 1 | 100.00 | |
| otbn_mem_gnt_acc_err | 1 | 1 | 100.00 | |||
| otbn_mem_gnt_acc_err | 16.000s | 78.185us | 1 | 1 | 100.00 | |
| otbn_non_sec_partial_wipe | 1 | 1 | 100.00 | |||
| otbn_partial_wipe | 6.000s | 30.277us | 1 | 1 | 100.00 | |
| tl_intg_err | 1 | 2 | 50.00 | |||
| otbn_tl_intg_err | 27.000s | 194.741us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| passthru_mem_tl_intg_err | 1 | 1 | 100.00 | |||
| otbn_passthru_mem_tl_intg_err | 24.000s | 729.753us | 1 | 1 | 100.00 | |
| prim_fsm_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| prim_count_check | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| otbn_smoke | 9.000s | 136.967us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_dmem_err | 7.000s | 67.320us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_imem_err | 9.000s | 97.396us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| otbn_tl_intg_err | 27.000s | 194.741us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 9.000s | 21.494us | 1 | 1 | 100.00 | |
| sec_cm_controller_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 9.000s | 97.396us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 67.320us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 31.975us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 5.000s | 14.274us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_controller_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_scramble_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 9.000s | 97.396us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 67.320us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 31.975us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 5.000s | 14.274us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_scramble_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_global_esc | 1 | 1 | 100.00 | |||
| otbn_escalate | 9.000s | 21.494us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_fsm_local_esc | 4 | 5 | 80.00 | |||
| otbn_imem_err | 9.000s | 97.396us | 1 | 1 | 100.00 | |
| otbn_dmem_err | 7.000s | 67.320us | 1 | 1 | 100.00 | |
| otbn_zero_state_err_urnd | 6.000s | 31.975us | 1 | 1 | 100.00 | |
| otbn_illegal_mem_acc | 5.000s | 14.274us | 1 | 1 | 100.00 | |
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_start_stop_ctrl_fsm_sparse | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_data_reg_sw_sca | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_redun | 1 | 1 | 100.00 | |||
| otbn_ctrl_redun | 7.000s | 36.631us | 1 | 1 | 100.00 | |
| sec_cm_pc_ctrl_flow_redun | 1 | 1 | 100.00 | |||
| otbn_pc_ctrl_flow_redun | 15.000s | 89.095us | 1 | 1 | 100.00 | |
| sec_cm_rnd_bus_consistency | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 14.000s | 83.960us | 1 | 1 | 100.00 | |
| sec_cm_rnd_rng_digest | 1 | 1 | 100.00 | |||
| otbn_rnd_sec_cm | 14.000s | 83.960us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_base_intg_err | 7.000s | 30.895us | 1 | 1 | 100.00 | |
| sec_cm_rf_base_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_stack_wr_ptr_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_rf_bignum_data_reg_sw_integrity | 1 | 1 | 100.00 | |||
| otbn_rf_bignum_intg_err | 8.000s | 746.075us | 1 | 1 | 100.00 | |
| sec_cm_rf_bignum_data_reg_sw_glitch_detect | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| sec_cm_loop_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 5.000s | 18.001us | 1 | 1 | 100.00 | |
| sec_cm_call_stack_addr_integrity | 1 | 1 | 100.00 | |||
| otbn_stack_addr_integ_chk | 5.000s | 18.001us | 1 | 1 | 100.00 | |
| sec_cm_start_stop_ctrl_state_consistency | 0 | 1 | 0.00 | |||
| otbn_sec_wipe_err | 8.000s | 61.328us | 0 | 1 | 0.00 | |
| sec_cm_data_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_instruction_mem_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_data_reg_sw_sec_wipe | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_write_mem_integrity | 1 | 1 | 100.00 | |||
| otbn_multi | 28.000s | 383.974us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_count | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_flow_sca | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_data_mem_sw_noaccess | 1 | 1 | 100.00 | |||
| otbn_sw_no_acc | 5.000s | 18.125us | 1 | 1 | 100.00 | |
| sec_cm_key_sideload | 1 | 1 | 100.00 | |||
| otbn_single | 6.000s | 20.466us | 1 | 1 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 0 | 1 | 0.00 | |||
| otbn_sec_cm | 11.000s | 58.099us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| otbn_stress_all_with_rand_reset | 138.000s | 1802.086us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed | ||||
| otbn_sec_wipe_err | 73867366273376958981229759845895938692713742778935384300189787090668099875514 | 108 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 61328242 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
UVM_ERROR @ 61328242 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 61328242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed | ||||
| otbn_sec_cm | 73644086579155009758245005809332193272053891169093307831760623463714991845758 | 113 |
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 58099299 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 58099299 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 58099299 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 58099299 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 58099299 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
|
|