Simulation Results: otp_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.14 %
  • code
  • 71.58 %
  • assert
  • 92.96 %
  • func
  • 51.87 %
  • line
  • 87.44 %
  • branch
  • 83.89 %
  • cond
  • 85.47 %
  • toggle
  • 63.99 %
  • FSM
  • 37.12 %
Validation stages
V1
90.91%
V2
76.00%
V2S
76.79%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.900s 109.299us 1 1 100.00
smoke 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.650s 246.714us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.640s 119.385us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 3.190s 86.891us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.800s 328.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.070s 158.157us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.640s 119.385us 1 1 100.00
otp_ctrl_csr_aliasing 4.800s 328.140us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.350s 157.018us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.470s 157.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 107.230s 2307.686us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.520s 165.017us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 3.150s 112.506us 0 1 0.00
otp_ctrl_check_fail 12.330s 528.055us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 5.600s 2140.481us 1 1 100.00
partition_lock 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.800s 532.743us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 11.210s 1753.281us 0 1 0.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 12.740s 621.244us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 14.580s 588.109us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 3.960s 283.491us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 21.470s 1785.863us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.510s 81.494us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.030s 916.180us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.940s 100.257us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.940s 100.257us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.650s 246.714us 1 1 100.00
otp_ctrl_csr_rw 2.640s 119.385us 1 1 100.00
otp_ctrl_csr_aliasing 4.800s 328.140us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.950s 368.669us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.650s 246.714us 1 1 100.00
otp_ctrl_csr_rw 2.640s 119.385us 1 1 100.00
otp_ctrl_csr_aliasing 4.800s 328.140us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.950s 368.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 14.000s 2160.525us 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 14.000s 2160.525us 1 1 100.00
sec_cm_secret_mem_scramble 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_part_mem_digest 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_macro_errs 14.580s 588.109us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_macro_errs 14.580s 588.109us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 25.430s 4315.034us 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.520s 165.017us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 12.330s 528.055us 0 1 0.00
sec_cm_part_mem_regren 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_part_mem_sw_unreadable 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_part_mem_sw_unwritable 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_lc_part_mem_sw_noaccess 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_access_ctrl_mubi 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 0 1 0.00
otp_ctrl_dai_lock 4.660s 1975.255us 0 1 0.00
sec_cm_test_bus_lc_gated 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 282.950s 62641.422us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 5.600s 2140.481us 1 1 100.00
sec_cm_check_trigger_config_regwen 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_check_config_regwen 0 1 0.00
otp_ctrl_smoke 2.480s 60.100us 0 1 0.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 14.580s 588.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 60.540s 22327.173us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.760s 32.735us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: *
otp_ctrl_smoke 46525403898793965846939948130487132799164212514422832753784190079723841017418 1813
UVM_ERROR @ 60099514 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 60099514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_partition_walk 55002685421688858256316112283727196518500121397447312064570665001424318157210 165258
UVM_ERROR @ 2307686150 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: 0x0
UVM_INFO @ 2307686150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 29610134794669941619706046462045776922663636213778599599970809489490414337930 86
UVM_ERROR @ 22327173154 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 22327173154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 21368985131612933472144417813900711244896979324187343034843441592393375896989 2257
UVM_ERROR @ 112505717 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 112505717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_lock 37413895173971340842883433717695895353120366778925185428722553985394165760888 2241
UVM_ERROR @ 1975254871 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 1975254871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state
otp_ctrl_parallel_lc_req 71300843322482295601806618049615933569300032276180793222834404083408682212234 10833
UVM_ERROR @ 1753280845 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (3 [0x3] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
UVM_INFO @ 1753280845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 113281029462332405922293843724013092461840155476873774305627439565543918642864 13325
UVM_ERROR @ 528054732 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32 [0x20]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 528054732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 76668945116747713234016850105468484780498210146307018182709055966357178160235 89
UVM_ERROR @ 32734625 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 32734625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:958) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask *
otp_ctrl_stress_all 32315016537484506830425587354618557086302911336558792429319547128955891943688 13911
UVM_ERROR @ 1785862788 ps: (otp_ctrl_scoreboard.sv:958) [uvm_test_top.env.scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (258 [0x102] vs 256 [0x100]) reg name: status, compare_mask 0
UVM_INFO @ 1785862788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---