Simulation Results: rom_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.91 %
  • code
  • 99.33 %
  • assert
  • 96.80 %
  • func
  • 97.61 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.92 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.050s 136.576us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.120s 171.206us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 5.360s 544.297us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.190s 388.380us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 554.843us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.800s 388.243us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 5.360s 544.297us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 554.843us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.960s 169.760us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.760s 499.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.410s 1058.714us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 12.520s 766.191us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.340s 243.895us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.710s 535.286us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.430s 164.897us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.430s 164.897us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.120s 171.206us 1 1 100.00
rom_ctrl_csr_rw 5.360s 544.297us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 554.843us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.410s 172.520us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.120s 171.206us 1 1 100.00
rom_ctrl_csr_rw 5.360s 544.297us 1 1 100.00
rom_ctrl_csr_aliasing 3.690s 554.843us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.410s 172.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.600s 1933.939us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
rom_ctrl_tl_intg_err 42.210s 894.963us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.050s 136.576us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.050s 136.576us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.050s 136.576us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 42.210s 894.963us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
rom_ctrl_kmac_err_chk 6.340s 243.895us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 55.160s 1469.788us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.600s 1933.939us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 198.060s 1036.531us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 319.870s 4055.633us 1 1 100.00

Error Messages

   Test seed line log context