Simulation Results: rstmgr

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.88 %
  • code
  • 99.20 %
  • assert
  • 97.44 %
  • func
  • 96.99 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.18 %
  • toggle
  • 99.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.710s 70.476us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.040s 63.800us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.680s 143.109us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.170s 44.995us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.580s 95.230us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00
rstmgr_csr_aliasing 1.170s 44.995us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.200s 102.040us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.520s 45.394us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.940s 37.570us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.370s 733.197us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.370s 733.197us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.370s 733.197us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.370s 733.197us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 25.040s 3559.647us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.930s 36.097us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.960s 44.424us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.960s 44.424us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.040s 63.800us 1 1 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00
rstmgr_csr_aliasing 1.170s 44.995us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 48.397us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.040s 63.800us 1 1 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00
rstmgr_csr_aliasing 1.170s 44.995us 1 1 100.00
rstmgr_same_csr_outstanding 1.420s 48.397us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 35.220s 7438.153us 1 1 100.00
rstmgr_tl_intg_err 2.630s 332.832us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 35.220s 7438.153us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 35.220s 7438.153us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.630s 332.832us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.540s 63.017us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.100s 450.281us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 2.460s 291.679us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 35.220s 7438.153us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.850s 37.446us 1 1 100.00

Error Messages

   Test seed line log context