Simulation Results: rv_timer

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.78 %
  • code
  • 99.53 %
  • assert
  • 96.82 %
  • func
  • 85.00 %
  • line
  • 99.64 %
  • branch
  • 100.00 %
  • cond
  • 98.46 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.650s 1270.702us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 41.382us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.660s 38.681us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.560s 352.094us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 27.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.400s 90.143us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.660s 38.681us 1 1 100.00
rv_timer_csr_aliasing 0.760s 27.330us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.010s 285.849us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.820s 1423.239us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 115.990s 105338.104us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 115.990s 105338.104us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.150s 1306.039us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.750s 33.780us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.650s 84.670us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.260s 153.783us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.260s 153.783us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 41.382us 1 1 100.00
rv_timer_csr_rw 0.660s 38.681us 1 1 100.00
rv_timer_csr_aliasing 0.760s 27.330us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 20.988us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 41.382us 1 1 100.00
rv_timer_csr_rw 0.660s 38.681us 1 1 100.00
rv_timer_csr_aliasing 0.760s 27.330us 1 1 100.00
rv_timer_same_csr_outstanding 0.590s 20.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.120s 95.271us 1 1 100.00
rv_timer_tl_intg_err 1.120s 288.889us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.120s 288.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.930s 152.108us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.800s 44.282us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 12.180s 1984.873us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 32121321210467915879035588042474334553920016363413126512708075260008279844448 72
UVM_FATAL @ 152108324 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xef5d6b04) == 0x1
UVM_INFO @ 152108324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 93720516211136744286806208694291203755746955891370573889681015289661719448040 72
UVM_FATAL @ 285848883 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x2e50a504) == 0x1
UVM_INFO @ 285848883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 64218774520088586862364459307022936597008565375257797124376796320020170519599 73
UVM_ERROR @ 44281988 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44281988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
rv_timer_stress_all_with_rand_reset 92884343849707874389702086585803191909116688697976084321846231614338040958461 223
UVM_ERROR @ 1984873122 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 1984873122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---