Simulation Results: spi_device

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.88 %
  • code
  • 93.14 %
  • assert
  • 94.30 %
  • func
  • 73.21 %
  • line
  • 99.05 %
  • branch
  • 98.23 %
  • cond
  • 95.70 %
  • toggle
  • 83.36 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
96.15%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 125.870s 51944.291us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.160s 70.158us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.660s 70.249us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 22.950s 3602.965us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.670s 640.214us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.590s 257.006us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.660s 70.249us 1 1 100.00
spi_device_csr_aliasing 5.670s 640.214us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.710s 31.304us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.730s 541.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.800s 50.899us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.680s 1.262us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.690s 3.749us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.250s 68.695us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.250s 68.695us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.630s 2231.926us 1 1 100.00
spi_device_tpm_sts_read 0.920s 146.068us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 16.740s 9335.224us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 4.790s 2778.188us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.330s 17344.514us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 9.330s 17344.514us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.410s 199.934us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.410s 199.934us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.410s 199.934us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.410s 199.934us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.410s 199.934us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.930s 704.948us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 9.840s 4352.986us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 9.840s 4352.986us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 9.840s 4352.986us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 4.090s 1963.984us 1 1 100.00
spi_device_read_buffer_direct 2.430s 71.435us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 9.840s 4352.986us 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 45.030s 23030.137us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.290s 287.293us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.290s 287.293us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 125.870s 51944.291us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 72.980s 146146.612us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 155.040s 110984.294us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.670s 196.232us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 27.112us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 1.690s 116.396us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 1.690s 116.396us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 70.158us 1 1 100.00
spi_device_csr_rw 1.660s 70.249us 1 1 100.00
spi_device_csr_aliasing 5.670s 640.214us 1 1 100.00
spi_device_same_csr_outstanding 3.520s 250.627us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.160s 70.158us 1 1 100.00
spi_device_csr_rw 1.660s 70.249us 1 1 100.00
spi_device_csr_aliasing 5.670s 640.214us 1 1 100.00
spi_device_same_csr_outstanding 3.520s 250.627us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 5.170s 1150.721us 1 1 100.00
spi_device_sec_cm 0.890s 39.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 5.170s 1150.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 50.930s 61259.668us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 2178821873906535766755509165937172966872499427273937919119658263862464752521 73
UVM_ERROR @ 1074482 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[110])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1074482 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1074482 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1006])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 101956130560852833378467258990546708542986588090672174249974417959626726058206 73
UVM_ERROR @ 1225253 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8c0f1a [100011000000111100011010] vs 0x0 [0])
UVM_ERROR @ 1319253 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7cfcd [1111100111111001101] vs 0x0 [0])
UVM_ERROR @ 1410253 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xed6ac4 [111011010110101011000100] vs 0x0 [0])
UVM_ERROR @ 1444253 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x76c13f [11101101100000100111111] vs 0x0 [0])
UVM_ERROR @ 1494253 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xabec7e [101010111110110001111110] vs 0x0 [0])