Simulation Results: spi_host

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.11 %
  • code
  • 94.86 %
  • assert
  • 93.54 %
  • func
  • 87.92 %
  • block
  • 96.64 %
  • line
  • 98.47 %
  • branch
  • 92.95 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 16.000s 906.456us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 17.206us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 15.850us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 62.163us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 25.353us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 51.133us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 15.850us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.353us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 37.928us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 19.664us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 310.032us 1 1 100.00
spi_host_error_cmd 1.000s 21.390us 1 1 100.00
spi_host_event 4.000s 134.943us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 77.030us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 77.030us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 77.030us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 90.341us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 50.080us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 77.030us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 77.030us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 16.000s 906.456us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 16.000s 906.456us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 119.044us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 471.085us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 19.000s 2008.065us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 261.431us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 310.032us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 22.636us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 17.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 50.341us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 50.341us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.206us 1 1 100.00
spi_host_csr_rw 1.000s 15.850us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.353us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 47.684us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 17.206us 1 1 100.00
spi_host_csr_rw 1.000s 15.850us 1 1 100.00
spi_host_csr_aliasing 1.000s 25.353us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 47.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 1.000s 194.398us 1 1 100.00
spi_host_tl_intg_err 2.000s 186.048us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 186.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 681.000s 94591.598us 1 1 100.00

Error Messages

   Test seed line log context