Simulation Results: sram_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.45 %
  • code
  • 95.90 %
  • assert
  • 95.83 %
  • func
  • 94.62 %
  • line
  • 99.11 %
  • branch
  • 97.52 %
  • cond
  • 92.17 %
  • toggle
  • 90.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 67.870s 5775.569us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.690s 16.097us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.660s 43.177us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.070s 68.925us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 23.421us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.750s 404.310us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.660s 43.177us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 23.421us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 92.350s 1980.691us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 121.120s 5237.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 266.400s 18927.107us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 270.800s 38534.183us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 927.990s 72395.086us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 39.760s 2235.196us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 50.520s 14685.746us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 367.620s 107504.588us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 10.930s 10193.461us 1 1 100.00
sram_ctrl_partial_access_b2b 280.330s 14982.153us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 48.080s 1531.760us 1 1 100.00
sram_ctrl_throughput_w_partial_write 42.680s 775.753us 1 1 100.00
sram_ctrl_throughput_w_readback 17.080s 1607.061us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 271.510s 1864.715us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.010s 349.092us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1965.880s 33833.031us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.760s 50.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.400s 504.213us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.400s 504.213us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 16.097us 1 1 100.00
sram_ctrl_csr_rw 0.660s 43.177us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 23.421us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 19.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.690s 16.097us 1 1 100.00
sram_ctrl_csr_rw 0.660s 43.177us 1 1 100.00
sram_ctrl_csr_aliasing 0.720s 23.421us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.660s 19.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.280s 29405.321us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
sram_ctrl_tl_intg_err 1.790s 443.665us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.790s 443.665us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 271.510s 1864.715us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 271.510s 1864.715us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.660s 43.177us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 367.620s 107504.588us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 367.620s 107504.588us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 367.620s 107504.588us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 50.520s 14685.746us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.450s 707.008us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 34.280s 29405.321us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.630s 7351.572us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 67.870s 5775.569us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 67.870s 5775.569us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 367.620s 107504.588us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 50.520s 14685.746us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 67.870s 5775.569us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.760s 4.190us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.160s 410.133us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 14819198037082753343491783097702867617631863168369040883238693877506377042877 96
UVM_ERROR @ 4189982 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 4189982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---