Simulation Results: sram_ctrl

 
16/12/2025 16:01:43 sha: de081ff json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.35 %
  • code
  • 85.62 %
  • assert
  • 95.51 %
  • func
  • 95.92 %
  • line
  • 96.28 %
  • branch
  • 93.18 %
  • cond
  • 90.82 %
  • toggle
  • 90.66 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
70.83%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 46.390s 3110.637us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 0.800s 72.875us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 0.860s 23.189us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 0.990s 103.317us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 46.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.290s 39.694us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 0.860s 23.189us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 46.625us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 7.270s 445.408us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.290s 58.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 284.390s 45717.345us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 218.940s 13593.254us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 57.650s 3656.049us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 293.620s 1622.418us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.570s 591.812us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 629.940s 217002.536us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 8.040s 565.698us 1 1 100.00
sram_ctrl_partial_access_b2b 336.150s 166750.621us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.360s 261.654us 1 1 100.00
sram_ctrl_throughput_w_partial_write 37.020s 131.605us 1 1 100.00
sram_ctrl_throughput_w_readback 35.400s 278.634us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 516.260s 52508.517us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 0.980s 37.867us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 790.280s 5414.874us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 0.640s 12.092us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 84.787us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 1.760s 84.787us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 72.875us 1 1 100.00
sram_ctrl_csr_rw 0.860s 23.189us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 46.625us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.730s 20.766us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 0.800s 72.875us 1 1 100.00
sram_ctrl_csr_rw 0.860s 23.189us 1 1 100.00
sram_ctrl_csr_aliasing 0.670s 46.625us 1 1 100.00
sram_ctrl_same_csr_outstanding 0.730s 20.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.470s 1491.456us 1 1 100.00
tl_intg_err 1 2 50.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
sram_ctrl_tl_intg_err 2.040s 990.807us 1 1 100.00
prim_count_check 0 1 0.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.040s 990.807us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 516.260s 52508.517us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 516.260s 52508.517us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 0.860s 23.189us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 629.940s 217002.536us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 629.940s 217002.536us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 629.940s 217002.536us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.570s 591.812us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.130s 184.739us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.470s 1491.456us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 0.910s 31.619us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 46.390s 3110.637us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 46.390s 3110.637us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 629.940s 217002.536us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 1 0.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.570s 591.812us 1 1 100.00
sec_cm_key_local_esc 0 1 0.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
sec_cm_init_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 46.390s 3110.637us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
sram_ctrl_sec_cm 0.610s 6.779us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 30.980s 526.896us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
sram_ctrl_readback_err 112805708317193220612645317496765664453728981258195681824657378760593615466917 95
UVM_ERROR @ 31619318 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x72) != exp (0x5d)
UVM_INFO @ 31619318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: *
sram_ctrl_sec_cm 31200340014854180204235501620298464658126223328380108946621288029972989264923 96
UVM_ERROR @ 6778661 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
UVM_INFO @ 6778661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---