| V1 |
|
100.00% |
| V2 |
|
97.06% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| uart_smoke | 0.810s | 107.759us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| uart_csr_hw_reset | 0.700s | 18.783us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| uart_csr_rw | 0.850s | 62.838us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| uart_csr_bit_bash | 1.210s | 131.849us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| uart_csr_aliasing | 0.880s | 30.771us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_csr_mem_rw_with_rand_reset | 0.990s | 436.939us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| uart_csr_rw | 0.850s | 62.838us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.880s | 30.771us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| base_random_seq | 1 | 1 | 100.00 | |||
| uart_tx_rx | 13.660s | 46972.121us | 1 | 1 | 100.00 | |
| parity | 2 | 2 | 100.00 | |||
| uart_smoke | 0.810s | 107.759us | 1 | 1 | 100.00 | |
| uart_tx_rx | 13.660s | 46972.121us | 1 | 1 | 100.00 | |
| parity_error | 2 | 2 | 100.00 | |||
| uart_intr | 58.080s | 227066.860us | 1 | 1 | 100.00 | |
| uart_rx_parity_err | 89.460s | 77208.235us | 1 | 1 | 100.00 | |
| watermark | 2 | 2 | 100.00 | |||
| uart_tx_rx | 13.660s | 46972.121us | 1 | 1 | 100.00 | |
| uart_intr | 58.080s | 227066.860us | 1 | 1 | 100.00 | |
| fifo_full | 1 | 1 | 100.00 | |||
| uart_fifo_full | 22.710s | 77016.351us | 1 | 1 | 100.00 | |
| fifo_overflow | 1 | 1 | 100.00 | |||
| uart_fifo_overflow | 12.800s | 87676.619us | 1 | 1 | 100.00 | |
| fifo_reset | 1 | 1 | 100.00 | |||
| uart_fifo_reset | 29.740s | 78548.687us | 1 | 1 | 100.00 | |
| rx_frame_err | 1 | 1 | 100.00 | |||
| uart_intr | 58.080s | 227066.860us | 1 | 1 | 100.00 | |
| rx_break_err | 1 | 1 | 100.00 | |||
| uart_intr | 58.080s | 227066.860us | 1 | 1 | 100.00 | |
| rx_timeout | 1 | 1 | 100.00 | |||
| uart_intr | 58.080s | 227066.860us | 1 | 1 | 100.00 | |
| perf | 1 | 1 | 100.00 | |||
| uart_perf | 54.240s | 8537.723us | 1 | 1 | 100.00 | |
| sys_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 3.660s | 2942.493us | 1 | 1 | 100.00 | |
| line_loopback | 1 | 1 | 100.00 | |||
| uart_loopback | 3.660s | 2942.493us | 1 | 1 | 100.00 | |
| rx_noise_filter | 0 | 1 | 0.00 | |||
| uart_noise_filter | 2.190s | 1323.405us | 0 | 1 | 0.00 | |
| rx_start_bit_filter | 1 | 1 | 100.00 | |||
| uart_rx_start_bit_filter | 1.520s | 4578.404us | 1 | 1 | 100.00 | |
| tx_overide | 1 | 1 | 100.00 | |||
| uart_tx_ovrd | 4.160s | 1237.205us | 1 | 1 | 100.00 | |
| rx_oversample | 1 | 1 | 100.00 | |||
| uart_rx_oversample | 40.020s | 6625.894us | 1 | 1 | 100.00 | |
| long_b2b_transfer | 1 | 1 | 100.00 | |||
| uart_long_xfer_wo_dly | 174.740s | 92236.072us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| uart_stress_all | 178.580s | 164184.501us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| uart_alert_test | 0.540s | 43.969us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| uart_intr_test | 0.560s | 41.457us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.360s | 81.912us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| uart_tl_errors | 1.360s | 81.912us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.700s | 18.783us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.850s | 62.838us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.880s | 30.771us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.660s | 53.887us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| uart_csr_hw_reset | 0.700s | 18.783us | 1 | 1 | 100.00 | |
| uart_csr_rw | 0.850s | 62.838us | 1 | 1 | 100.00 | |
| uart_csr_aliasing | 0.880s | 30.771us | 1 | 1 | 100.00 | |
| uart_same_csr_outstanding | 0.660s | 53.887us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| uart_sec_cm | 0.790s | 124.519us | 1 | 1 | 100.00 | |
| uart_tl_intg_err | 0.850s | 169.165us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| uart_tl_intg_err | 0.850s | 169.165us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| uart_stress_all_with_rand_reset | 11.830s | 1827.619us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * | ||||
| uart_noise_filter | 18890316967121471677883023894441435475682954425149761885110077113772732340243 | 71 |
UVM_ERROR @ 113679750 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 113689954 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 113771586 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 147210094 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0
UVM_ERROR @ 147220298 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
|
|