Simulation Results: ac_range_check

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 82.89 %
  • code
  • 93.10 %
  • assert
  • 97.63 %
  • func
  • 57.93 %
  • block
  • 99.21 %
  • line
  • 99.94 %
  • branch
  • 98.35 %
  • toggle
  • 81.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 21.000s 1144.305us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 45.000s 2320.415us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 53.596us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 3.000s 23.290us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 32.000s 6557.275us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3979.784us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 2.000s 93.728us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 3.000s 23.290us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3979.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 2.000s 45.548us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 33.000s 5441.155us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 58.000s 7253.115us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 2.000s 24.526us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 2.000s 16.644us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 3.000s 146.887us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 3.000s 146.887us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 53.596us 1 1 100.00
ac_range_check_csr_rw 3.000s 23.290us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3979.784us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 133.274us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 3.000s 53.596us 1 1 100.00
ac_range_check_csr_rw 3.000s 23.290us 1 1 100.00
ac_range_check_csr_aliasing 19.000s 3979.784us 1 1 100.00
ac_range_check_same_csr_outstanding 4.000s 133.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3256.213us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3256.213us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3256.213us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 13.000s 3256.213us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 61.000s 22988.803us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 3.000s 19.484us 1 1 100.00
ac_range_check_tl_intg_err 8.000s 753.272us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 254.000s 11556.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 22.000s 1632.472us 1 1 100.00

Error Messages

   Test seed line log context