Simulation Results: aes

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.25 %
  • code
  • 92.52 %
  • assert
  • 98.39 %
  • func
  • 79.84 %
  • block
  • 94.44 %
  • line
  • 95.43 %
  • branch
  • 87.55 %
  • toggle
  • 97.99 %
  • FSM
  • 89.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 60.878us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 67.059us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 3.000s 206.949us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 59.924us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 293.449us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 107.278us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 60.788us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 59.924us 1 1 100.00
aes_csr_aliasing 2.000s 107.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 67.059us 1 1 100.00
aes_config_error 6.000s 355.973us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 67.059us 1 1 100.00
aes_config_error 6.000s 355.973us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
back2back 2 2 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
aes_b2b 23.000s 1458.625us 1 1 100.00
backpressure 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 67.059us 1 1 100.00
aes_config_error 6.000s 355.973us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 69.289us 1 1 100.00
aes_config_error 6.000s 355.973us 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 124.157us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 12.000s 220.813us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
stress 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
sideload 2 2 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
aes_sideload 4.000s 169.685us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 7.000s 871.460us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 41.000s 1695.022us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 65.465us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 4.000s 94.604us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 4.000s 94.604us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 3.000s 206.949us 1 1 100.00
aes_csr_rw 1.000s 59.924us 1 1 100.00
aes_csr_aliasing 2.000s 107.278us 1 1 100.00
aes_same_csr_outstanding 2.000s 150.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 3.000s 206.949us 1 1 100.00
aes_csr_rw 1.000s 59.924us 1 1 100.00
aes_csr_aliasing 2.000s 107.278us 1 1 100.00
aes_same_csr_outstanding 2.000s 150.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 141.524us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 151.409us 1 1 100.00
tl_intg_err 2 2 100.00
aes_tl_intg_err 3.000s 129.151us 1 1 100.00
aes_sec_cm 6.000s 2026.725us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 129.151us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 67.059us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
aes_core_fi 2.000s 86.143us 1 1 100.00
sec_cm_gcm_config_sparse 2 2 100.00
aes_config_error 6.000s 355.973us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 3.000s 296.733us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 60.975us 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
aes_sideload 4.000s 169.685us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.975us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 60.975us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 60.975us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 60.975us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 60.975us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 21.000s 1021.351us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 4.000s 93.533us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 4.000s 93.533us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 4.000s 93.533us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 91.292us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_ctr_fi 2.000s 48.984us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 4.000s 93.533us 1 1 100.00
aes_control_fi 2.000s 151.743us 1 1 100.00
aes_cipher_fi 2.000s 55.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 8.000s 159.931us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 22007805792741160808072980861444527001993098545744408279438597186409935614938 376
UVM_FATAL @ 159931425 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
UVM_INFO @ 159931425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---