Simulation Results: clkmgr

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 74.55 %
  • code
  • 69.44 %
  • assert
  • 88.64 %
  • func
  • 65.58 %
  • line
  • 82.34 %
  • branch
  • 87.58 %
  • cond
  • 77.68 %
  • toggle
  • 99.62 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
57.89%
V2S
52.94%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.620s 126.006us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.750s 21.669us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.860s 39.506us 0 1 0.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.700s 158.058us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.580s 2.329us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
clkmgr_csr_aliasing 1.700s 158.058us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.950s 50.447us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.910s 31.961us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.690s 17.414us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.620s 126.006us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.630s 8.915us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.590s 4.004us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.630s 8.915us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.920s 33.623us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 27.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 4.380s 405.162us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 4.380s 405.162us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 0.750s 21.669us 1 1 100.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
clkmgr_csr_aliasing 1.700s 158.058us 1 1 100.00
clkmgr_same_csr_outstanding 0.580s 2.447us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 0.750s 21.669us 1 1 100.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
clkmgr_csr_aliasing 1.700s 158.058us 1 1 100.00
clkmgr_same_csr_outstanding 0.580s 2.447us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 2.390s 203.129us 1 1 100.00
clkmgr_tl_intg_err 0.640s 10.587us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 42.827us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 42.827us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 42.827us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 42.827us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.630s 5.226us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.640s 10.587us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.630s 8.915us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.590s 4.004us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 0.980s 42.827us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.810s 25.350us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 2.390s 203.129us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.600s 4.483us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 2.390s 203.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.610s 7.750us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 0.670s 3.943us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b*
clkmgr_frequency 94226973108994897516829346249019053766322437178366918620239587540821865218495 72
UVM_ERROR @ 8915287 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 8915287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 100696350562514605665485565012879138260486417105038407795817300547261617289505 101
UVM_ERROR @ 33623163 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected 0b10, got 0b00
UVM_INFO @ 33623163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b*
clkmgr_frequency_timeout 50868516143950745358176362105228191536427982886047611866206611576958145951143 75
UVM_ERROR @ 4004466 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
UVM_INFO @ 4004466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 36222093841152192667138125364716415041803864416500900403946726403140229685272 76
UVM_ERROR @ 3942514 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
UVM_INFO @ 3942514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
clkmgr_regwen 94707406567589000048610237383043324392547049328621102626513622233946509911021 71
UVM_ERROR @ 7750231 ps: (clkmgr_scoreboard.sv:257) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (60554 [0xec8a] vs 64129 [0xfa81]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed
UVM_INFO @ 7750231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: *
clkmgr_shadow_reg_errors_with_csr_rw 106459158429054556736463406687520121617198458114761696319010318240275244477675 72
UVM_ERROR @ 5225541 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1
UVM_INFO @ 5225541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: *
clkmgr_tl_intg_err 46547065368915286774886913631336711013142800388440682902834930463069824548825 75
UVM_ERROR @ 10586522 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 10586522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 54256471459327912044516703335437624903523854472478209284844478375359414835628 72
UVM_ERROR @ 4483105 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 4483105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 30544591068851342334743999343260927144809503703078229795113603942437308668639 73
UVM_ERROR @ 2329240 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: 0x1
UVM_INFO @ 2329240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: *
clkmgr_csr_bit_bash 73921282897596283214806559877811390894357401730208366459762259114030696044922 72
UVM_ERROR @ 39505556 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: 0x1 Wrote clkmgr_reg_block.measure_ctrl_regwen[0]: 0
UVM_INFO @ 39505556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:642) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
clkmgr_same_csr_outstanding 44814085298196932786021778118517183580679478699312452410874290324084736265112 72
UVM_ERROR @ 2447049 ps: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x55293d64 read out mismatch
UVM_INFO @ 2447049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---