Simulation Results: dma

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 81.71 %
  • code
  • 91.47 %
  • assert
  • 95.87 %
  • func
  • 57.78 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 83.12 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 5.000s 936.696us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 5.000s 279.210us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 4.000s 273.793us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 27.898us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 22.942us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 1528.716us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 6.000s 445.922us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 47.392us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 22.942us 1 1 100.00
dma_csr_aliasing 6.000s 445.922us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 127.000s 30352.901us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 245.000s 103180.778us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 137.000s 26310.346us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 137.000s 26310.346us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 245.000s 103180.778us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 196.000s 14996.231us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 137.000s 26310.346us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 705.211us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 86.000s 37860.370us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 40.205us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 33.491us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 101.300us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 101.300us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 27.898us 1 1 100.00
dma_csr_rw 2.000s 22.942us 1 1 100.00
dma_csr_aliasing 6.000s 445.922us 1 1 100.00
dma_same_csr_outstanding 2.000s 109.067us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 27.898us 1 1 100.00
dma_csr_rw 2.000s 22.942us 1 1 100.00
dma_csr_aliasing 6.000s 445.922us 1 1 100.00
dma_same_csr_outstanding 2.000s 109.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 18.000s 816.764us 1 1 100.00
dma_generic_stress 196.000s 14996.231us 1 1 100.00
dma_handshake_stress 137.000s 26310.346us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 7.000s 3174.188us 1 1 100.00
tl_intg_err 2 2 100.00
dma_sec_cm 1.000s 32.182us 1 1 100.00
dma_tl_intg_err 2.000s 54.092us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 48.000s 2480.405us 1 1 100.00
dma_longer_transfer 3.000s 122.457us 1 1 100.00
dma_stress_all_with_rand_reset 24.000s 1956.401us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
dma_stress_all_with_rand_reset 111059169681436235856848694279355480450498003449060171664767042229181294307928 133
UVM_ERROR @ 1956400980ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1956400980ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---