Simulation Results: edn

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.51 %
  • code
  • 80.59 %
  • assert
  • 94.79 %
  • func
  • 81.15 %
  • line
  • 97.55 %
  • branch
  • 91.49 %
  • cond
  • 85.32 %
  • toggle
  • 76.42 %
  • FSM
  • 52.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.100s 18.552us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 67.470us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.860s 25.210us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.490s 867.060us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.010s 61.740us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.440s 103.742us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.860s 25.210us 1 1 100.00
edn_csr_aliasing 1.010s 61.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.230s 70.421us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.230s 70.421us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.230s 70.421us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.160s 22.087us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.170s 31.371us 1 1 100.00
errs 1 1 100.00
edn_err 1.120s 25.960us 1 1 100.00
disable 2 2 100.00
edn_disable 1.150s 23.703us 1 1 100.00
edn_disable_auto_req_mode 0.900s 79.292us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.210s 91.710us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.010s 14.492us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.050s 43.601us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.630s 43.639us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.630s 43.639us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 67.470us 1 1 100.00
edn_csr_rw 0.860s 25.210us 1 1 100.00
edn_csr_aliasing 1.010s 61.740us 1 1 100.00
edn_same_csr_outstanding 1.050s 26.057us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 67.470us 1 1 100.00
edn_csr_rw 0.860s 25.210us 1 1 100.00
edn_csr_aliasing 1.010s 61.740us 1 1 100.00
edn_same_csr_outstanding 1.050s 26.057us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
edn_tl_intg_err 2.770s 144.247us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.910s 44.543us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.170s 31.371us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.170s 31.371us 1 1 100.00
edn_sec_cm 3.780s 491.132us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.170s 31.371us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.770s 144.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 35.380s 4310.410us 1 1 100.00

Error Messages

   Test seed line log context