Simulation Results: edn

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.08 %
  • code
  • 82.43 %
  • assert
  • 96.88 %
  • func
  • 81.93 %
  • line
  • 98.33 %
  • branch
  • 93.51 %
  • cond
  • 89.85 %
  • toggle
  • 87.29 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.950s 52.625us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 29.697us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 48.609us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.220s 100.097us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.830s 17.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 80.452us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 48.609us 1 1 100.00
edn_csr_aliasing 0.830s 17.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.990s 194.950us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.990s 194.950us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.990s 194.950us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 24.030us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.140s 27.311us 1 1 100.00
errs 1 1 100.00
edn_err 0.930s 25.218us 1 1 100.00
disable 2 2 100.00
edn_disable 1.010s 23.273us 1 1 100.00
edn_disable_auto_req_mode 1.100s 443.757us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.720s 1113.675us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 29.273us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 14.575us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.520s 23.477us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.520s 23.477us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 29.697us 1 1 100.00
edn_csr_rw 0.770s 48.609us 1 1 100.00
edn_csr_aliasing 0.830s 17.937us 1 1 100.00
edn_same_csr_outstanding 0.950s 79.735us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 29.697us 1 1 100.00
edn_csr_rw 0.770s 48.609us 1 1 100.00
edn_csr_aliasing 0.830s 17.937us 1 1 100.00
edn_same_csr_outstanding 0.950s 79.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.730s 263.385us 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 27.299us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.140s 27.311us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.140s 27.311us 1 1 100.00
edn_sec_cm 2.590s 677.077us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.140s 27.311us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.730s 263.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 34.500s 12463.287us 1 1 100.00

Error Messages

   Test seed line log context