Simulation Results: hmac

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.09 %
  • code
  • 97.10 %
  • assert
  • 96.42 %
  • func
  • 43.75 %
  • line
  • 99.68 %
  • branch
  • 98.84 %
  • cond
  • 95.78 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.190s 327.673us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.750s 19.351us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.630s 19.899us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.540s 314.569us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.280s 378.913us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.990s 45.169us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.630s 19.899us 1 1 100.00
hmac_csr_aliasing 5.280s 378.913us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 38.890s 1194.361us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.180s 161.634us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.030s 176.359us 1 1 100.00
hmac_test_sha384_vectors 19.160s 268.590us 1 1 100.00
hmac_test_sha512_vectors 19.240s 249.970us 1 1 100.00
hmac_test_hmac256_vectors 8.510s 301.998us 1 1 100.00
hmac_test_hmac384_vectors 9.040s 319.774us 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1443.175us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.470s 37.501us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 818.620s 20994.771us 1 1 100.00
error 1 1 100.00
hmac_error 7.620s 3322.111us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 31.190s 10707.678us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.190s 327.673us 1 1 100.00
hmac_long_msg 38.890s 1194.361us 1 1 100.00
hmac_back_pressure 6.180s 161.634us 1 1 100.00
hmac_datapath_stress 818.620s 20994.771us 1 1 100.00
hmac_burst_wr 1.470s 37.501us 1 1 100.00
hmac_stress_all 229.290s 23111.099us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.190s 327.673us 1 1 100.00
hmac_long_msg 38.890s 1194.361us 1 1 100.00
hmac_back_pressure 6.180s 161.634us 1 1 100.00
hmac_datapath_stress 818.620s 20994.771us 1 1 100.00
hmac_wipe_secret 31.190s 10707.678us 1 1 100.00
hmac_test_sha256_vectors 8.030s 176.359us 1 1 100.00
hmac_test_sha384_vectors 19.160s 268.590us 1 1 100.00
hmac_test_sha512_vectors 19.240s 249.970us 1 1 100.00
hmac_test_hmac256_vectors 8.510s 301.998us 1 1 100.00
hmac_test_hmac384_vectors 9.040s 319.774us 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1443.175us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.190s 327.673us 1 1 100.00
hmac_long_msg 38.890s 1194.361us 1 1 100.00
hmac_back_pressure 6.180s 161.634us 1 1 100.00
hmac_datapath_stress 818.620s 20994.771us 1 1 100.00
hmac_burst_wr 1.470s 37.501us 1 1 100.00
hmac_error 7.620s 3322.111us 1 1 100.00
hmac_wipe_secret 31.190s 10707.678us 1 1 100.00
hmac_test_sha256_vectors 8.030s 176.359us 1 1 100.00
hmac_test_sha384_vectors 19.160s 268.590us 1 1 100.00
hmac_test_sha512_vectors 19.240s 249.970us 1 1 100.00
hmac_test_hmac256_vectors 8.510s 301.998us 1 1 100.00
hmac_test_hmac384_vectors 9.040s 319.774us 1 1 100.00
hmac_test_hmac512_vectors 10.830s 1443.175us 1 1 100.00
hmac_stress_all 229.290s 23111.099us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 229.290s 23111.099us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 38.494us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.610s 47.562us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.250s 615.591us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.250s 615.591us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.750s 19.351us 1 1 100.00
hmac_csr_rw 0.630s 19.899us 1 1 100.00
hmac_csr_aliasing 5.280s 378.913us 1 1 100.00
hmac_same_csr_outstanding 1.040s 113.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.750s 19.351us 1 1 100.00
hmac_csr_rw 0.630s 19.899us 1 1 100.00
hmac_csr_aliasing 5.280s 378.913us 1 1 100.00
hmac_same_csr_outstanding 1.040s 113.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.750s 73.374us 1 1 100.00
hmac_tl_intg_err 2.220s 313.346us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.220s 313.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.190s 327.673us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.740s 43.801us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 26.050s 7682.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.340s 418.446us 1 1 100.00

Error Messages

   Test seed line log context