i2c Simulation Results

Simulation Results: i2c

17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.05 %

code
81.60 %

assert
96.41 %

func
80.13 %

line
96.41 %

branch
92.41 %

cond
84.86 %

toggle
89.66 %

FSM
44.64 %

Validation stages

V1		100.00%
V2		91.84%
V2S		100.00%
V3		0.00%

9/9 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	17.890s	1460.922us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	11.380s	3331.313us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.680s	28.526us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.720s	25.132us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	1.990s	282.690us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.320s	40.630us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.810s	35.438us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.720s	25.132us	1	1	100.00
	i2c_csr_aliasing	1.320s	40.630us	1	1	100.00

45/49 passed

91.84 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.820s	196.232us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	360.710s	15700.883us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	89.530s	3426.605us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.630s	27.639us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	49.940s	3064.085us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	26.070s	5673.705us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.890s	439.495us	1	1	100.00
	i2c_host_fifo_fmt_empty	4.970s	699.049us	1	1	100.00
	i2c_host_fifo_reset_rx	5.610s	293.521us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	39.980s	3531.369us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	9.630s	791.102us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	1.240s	306.160us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.760s	474.060us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	1132.920s	68497.189us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.000s	6150.118us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	19.980s	1582.045us	1	1	100.00
	i2c_target_intr_smoke	4.830s	3533.875us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.170s	252.639us	1	1	100.00
	i2c_target_fifo_reset_tx	0.930s	194.433us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	6.980s	9392.714us	1	1	100.00
	i2c_target_stress_rd	19.980s	1582.045us	1	1	100.00
	i2c_target_intr_stress_wr	20.700s	11256.044us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.690s	22642.170us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	6.380s	2957.124us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.980s	6487.937us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	3.540s	10386.422us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.110s	7083.851us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.890s	454.710us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	89.530s	3426.605us	1	1	100.00
	i2c_host_perf_precise	131.620s	24307.317us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	9.630s	791.102us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.420s	97.985us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.930s	3055.993us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.800s	437.178us	1	1	100.00
	i2c_target_nack_txstretch	1.050s	581.075us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	3.260s	342.557us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.540s	5184.729us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.600s	110.944us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.570s	40.249us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.070s	195.405us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.070s	195.405us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	28.526us	1	1	100.00
	i2c_csr_rw	0.720s	25.132us	1	1	100.00
	i2c_csr_aliasing	1.320s	40.630us	1	1	100.00
	i2c_same_csr_outstanding	1.040s	168.381us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.680s	28.526us	1	1	100.00
	i2c_csr_rw	0.720s	25.132us	1	1	100.00
	i2c_csr_aliasing	1.320s	40.630us	1	1	100.00
	i2c_same_csr_outstanding	1.040s	168.381us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.070s	105.492us	1	1	100.00
	i2c_sec_cm	0.940s	71.185us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.070s	105.492us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	18.310s	556.279us	1
target_error_intr				1
	i2c_target_unexp_stop	1.300s	118.092us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	4.940s	1099.689us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	56963510082955622861864726055232830243095285578325809564817856982140836714548	115	UVM_ERROR @ 196231974 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 196231974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	80294156907593219518675913664833757997455288444843037855522109494429677665987	137	UVM_ERROR @ 15700883073 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 15700883073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	34210737381481769740577070423547608850735686348133073274559541977439793485592	87	UVM_ERROR @ 1099688847 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between UVM_INFO @ 1099688847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	57255773131631293894173086551060077172754328837601314614804686449500660542614	81	UVM_ERROR @ 474060138 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between UVM_INFO @ 474060138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	100838362857650055358309161156668529339010941720791565567649946882607028620091	75	UVM_ERROR @ 118091924 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 167 [0xa7]) UVM_INFO @ 118091924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	103625239127053541478165071460171746234837551900198781378259943554489932084765	76	UVM_FATAL @ 10386421821 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! UVM_INFO @ 10386421821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	77545877082369901801415354581236103404621792146774815534475255480576679643211	85	UVM_ERROR @ 556278636 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 556278636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---