Simulation Results: keymgr

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.54 %
  • code
  • 95.56 %
  • assert
  • 97.49 %
  • func
  • 69.57 %
  • line
  • 98.78 %
  • branch
  • 98.03 %
  • cond
  • 94.71 %
  • toggle
  • 97.89 %
  • FSM
  • 88.37 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.900s 338.788us 1 1 100.00
random 1 1 100.00
keymgr_random 4.270s 265.623us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.070s 18.075us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.670s 143.822us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 8.140s 1817.098us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.940s 38.896us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
keymgr_csr_aliasing 8.140s 1817.098us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 6.170s 538.032us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.620s 21.642us 1 1 100.00
keymgr_sideload_kmac 1.990s 39.599us 1 1 100.00
keymgr_sideload_aes 2.790s 150.731us 1 1 100.00
keymgr_sideload_otbn 1.950s 63.947us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.200s 347.104us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.350s 67.093us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.190s 82.874us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.140s 74.534us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 77.273us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.280s 99.314us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 38.870s 5402.933us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.890s 40.312us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.820s 35.276us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 3.210s 874.289us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 3.210s 874.289us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.070s 18.075us 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
keymgr_csr_aliasing 8.140s 1817.098us 1 1 100.00
keymgr_same_csr_outstanding 1.430s 385.218us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.070s 18.075us 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
keymgr_csr_aliasing 8.140s 1817.098us 1 1 100.00
keymgr_same_csr_outstanding 1.430s 385.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
keymgr_tl_intg_err 7.320s 394.355us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.660s 725.800us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.660s 725.800us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.660s 725.800us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.660s 725.800us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.930s 383.095us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.320s 394.355us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.660s 725.800us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 6.170s 538.032us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 4.270s 265.623us 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 4.270s 265.623us 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 4.270s 265.623us 1 1 100.00
keymgr_csr_rw 0.920s 11.951us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.350s 67.093us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 77.273us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.620s 77.273us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.270s 265.623us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 6.970s 1847.969us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.910s 154.041us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.350s 67.093us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.910s 154.041us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.910s 154.041us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.910s 154.041us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.910s 4424.835us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.910s 154.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
keymgr_stress_all_with_rand_reset 9.150s 514.280us 1 1 100.00

Error Messages

   Test seed line log context