Simulation Results: kmac

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.62 %
  • code
  • 88.64 %
  • assert
  • 97.58 %
  • func
  • 91.65 %
  • line
  • 97.27 %
  • branch
  • 95.33 %
  • cond
  • 93.58 %
  • toggle
  • 100.00 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 38.850s 1028.952us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.040s 21.708us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.910s 28.538us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 10.620s 3129.993us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 2.980s 82.035us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.970s 82.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.910s 28.538us 1 1 100.00
kmac_csr_aliasing 2.980s 82.035us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.830s 62.018us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.490s 273.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1324.570s 107307.902us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 357.610s 18256.324us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 33.450s 8420.163us 1 1 100.00
kmac_test_vectors_sha3_256 24.570s 587.266us 1 1 100.00
kmac_test_vectors_sha3_384 17.710s 839.812us 1 1 100.00
kmac_test_vectors_sha3_512 561.380s 35124.361us 1 1 100.00
kmac_test_vectors_shake_128 1461.450s 69696.360us 1 1 100.00
kmac_test_vectors_shake_256 1183.360s 42008.475us 1 1 100.00
kmac_test_vectors_kmac 2.000s 98.352us 1 1 100.00
kmac_test_vectors_kmac_xof 1.420s 52.055us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 289.480s 74447.656us 1 1 100.00
app 1 1 100.00
kmac_app 75.450s 2014.250us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 38.880s 1983.406us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 259.820s 73894.993us 1 1 100.00
error 1 1 100.00
kmac_error 100.410s 6485.651us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.130s 1250.619us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 56.130s 10170.663us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 22.160s 1853.547us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 7.910s 1414.559us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 2.110s 142.266us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.410s 40.444us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 372.770s 72906.109us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.680s 14.495us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.120s 16.575us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.780s 143.967us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.780s 143.967us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.040s 21.708us 1 1 100.00
kmac_csr_rw 0.910s 28.538us 1 1 100.00
kmac_csr_aliasing 2.980s 82.035us 1 1 100.00
kmac_same_csr_outstanding 2.190s 205.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.040s 21.708us 1 1 100.00
kmac_csr_rw 0.910s 28.538us 1 1 100.00
kmac_csr_aliasing 2.980s 82.035us 1 1 100.00
kmac_same_csr_outstanding 2.190s 205.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 108.760us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.180s 108.760us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.180s 108.760us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.180s 108.760us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.330s 1273.307us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 3.320s 447.402us 1 1 100.00
kmac_sec_cm 27.750s 4720.684us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.320s 447.402us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.410s 40.444us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 38.850s 1028.952us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 289.480s 74447.656us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.180s 108.760us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 27.750s 4720.684us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 27.750s 4720.684us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 27.750s 4720.684us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 38.850s 1028.952us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.410s 40.444us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 27.750s 4720.684us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 221.790s 15487.332us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 38.850s 1028.952us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 161.210s 17768.072us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17)
kmac_sideload_invalid 6824615509831019892558511665586677990370418064026981663147787105650338802273 92
UVM_FATAL @ 10170663226 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf8bc0000, Comparison=CompareOpEq, exp_data=0x1, call_count=17)
UVM_INFO @ 10170663226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---