Simulation Results: lc_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.71 %
  • code
  • 86.33 %
  • assert
  • 95.99 %
  • func
  • 83.81 %
  • line
  • 97.64 %
  • branch
  • 96.13 %
  • cond
  • 79.10 %
  • toggle
  • 82.58 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
85.00%
V2S
64.29%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.350s 238.359us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.760s 18.559us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 22.644us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 51.573us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 16.943us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.100s 26.444us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 22.644us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 16.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 1.230s 26.439us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 2.970s 644.372us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.670s 113.245us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.730s 255.066us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.670s 453.850us 1 1 100.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_prog_failure 1.730s 255.066us 1 1 100.00
lc_ctrl_errors 5.670s 453.850us 1 1 100.00
lc_ctrl_security_escalation 6.760s 936.662us 1 1 100.00
lc_ctrl_jtag_state_failure 5.970s 78.546us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.720s 494.801us 1 1 100.00
lc_ctrl_jtag_errors 41.700s 12725.643us 1 1 100.00
jtag_access 12 13 92.31
lc_ctrl_jtag_csr_hw_reset 1.110s 1304.987us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.880s 274.542us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 25.310s 1662.325us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.610s 286.076us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.230s 605.015us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.770s 458.767us 1 1 100.00
lc_ctrl_jtag_alert_test 0.880s 33.892us 1 1 100.00
lc_ctrl_jtag_smoke 1.240s 136.244us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.520s 305.149us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.720s 494.801us 1 1 100.00
lc_ctrl_jtag_errors 41.700s 12725.643us 1 1 100.00
lc_ctrl_jtag_access 6.200s 727.379us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 18.970s 1010.296us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.620s 454.766us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 34.220us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 40.630s 30233.245us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.910s 18.055us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.570s 476.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.570s 476.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 18.559us 1 1 100.00
lc_ctrl_csr_rw 0.800s 22.644us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 16.943us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.050s 97.508us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.760s 18.559us 1 1 100.00
lc_ctrl_csr_rw 0.800s 22.644us 1 1 100.00
lc_ctrl_csr_aliasing 0.870s 16.943us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.050s 97.508us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.080s 390.534us 1 1 100.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.080s 390.534us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 2.970s 644.372us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 5.260s 73.913us 0 1 0.00
lc_ctrl_sec_cm 7.910s 248.227us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.760s 936.662us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 1.230s 26.439us 0 1 0.00
lc_ctrl_jtag_state_post_trans 10.520s 305.149us 0 1 0.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.190s 975.869us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.190s 975.869us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.040s 247.389us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.930s 957.121us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.930s 957.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 6.040s 555.288us 0 1 0.00

Error Messages

   Test seed line log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
lc_ctrl_state_failure 110574974310675365985892028912883343245629992783419598240918610094084058306312 1094
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 73913342 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 73913342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_state_post_trans 86934754766892852772921978027699973931411347382466976837840192923101139038384 210
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 26439082 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 26439082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 100083882334107089039272498999138413232635568117271300027412425440733540127915 333
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 78546140 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 78546140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 98236507724283125832482312299909526587068297641531384601506204165811983888361 650
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 305149353 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 305149353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 106848936629858955731925853914857608712680614447070098774869490185816293834882 4301
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 30233245038 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 30233245038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76677212091777435714687637953928264338504666208153791285106350095094346494622 330
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 555288024 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 555288024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---