lc_ctrl Simulation Results

Simulation Results: lc_ctrl

17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
89.70 %

code
87.28 %

assert
95.85 %

func
85.97 %

line
97.39 %

branch
95.38 %

cond
79.15 %

toggle
80.76 %

FSM
83.72 %

Validation stages

V1		100.00%
V2		85.00%
V2S		64.29%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	lc_ctrl_smoke	1.730s	794.234us	1	1	100.00
csr_hw_reset				1	1	100.00
	lc_ctrl_csr_hw_reset	0.980s	54.707us	1	1	100.00
csr_rw				1	1	100.00
	lc_ctrl_csr_rw	0.900s	123.574us	1	1	100.00
csr_bit_bash				1	1	100.00
	lc_ctrl_csr_bit_bash	1.190s	89.997us	1	1	100.00
csr_aliasing				1	1	100.00
	lc_ctrl_csr_aliasing	0.810s	82.597us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	lc_ctrl_csr_mem_rw_with_rand_reset	1.100s	95.389us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	lc_ctrl_csr_rw	0.900s	123.574us	1	1	100.00
	lc_ctrl_csr_aliasing	0.810s	82.597us	1	1	100.00

34/40 passed

85.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
state_post_trans				0	1	0.00
	lc_ctrl_state_post_trans	1.480s	47.363us	0	1	0.00
regwen_during_op				1	1	100.00
	lc_ctrl_regwen_during_op	14.700s	342.096us	1	1	100.00
rand_wr_claim_transition_if				1	1	100.00
	lc_ctrl_claim_transition_if	0.760s	14.757us	1	1	100.00
lc_prog_failure				1	1	100.00
	lc_ctrl_prog_failure	1.630s	76.671us	1	1	100.00
lc_state_failure				0	1	0.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
lc_errors				1	1	100.00
	lc_ctrl_errors	5.320s	423.658us	1	1	100.00
security_escalation				5	7	71.43
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_prog_failure	1.630s	76.671us	1	1	100.00
	lc_ctrl_errors	5.320s	423.658us	1	1	100.00
	lc_ctrl_security_escalation	4.780s	1321.806us	1	1	100.00
	lc_ctrl_jtag_state_failure	13.660s	508.083us	0	1	0.00
	lc_ctrl_jtag_prog_failure	3.690s	1249.243us	1	1	100.00
	lc_ctrl_jtag_errors	52.420s	3057.986us	1	1	100.00
jtag_access				12	13	92.31
	lc_ctrl_jtag_csr_hw_reset	1.550s	168.130us	1	1	100.00
	lc_ctrl_jtag_csr_rw	1.470s	121.269us	1	1	100.00
	lc_ctrl_jtag_csr_bit_bash	4.320s	1155.169us	1	1	100.00
	lc_ctrl_jtag_csr_aliasing	3.200s	408.835us	1	1	100.00
	lc_ctrl_jtag_same_csr_outstanding	1.420s	35.800us	1	1	100.00
	lc_ctrl_jtag_csr_mem_rw_with_rand_reset	2.020s	359.755us	1	1	100.00
	lc_ctrl_jtag_alert_test	1.550s	355.187us	1	1	100.00
	lc_ctrl_jtag_smoke	4.000s	195.881us	1	1	100.00
	lc_ctrl_jtag_state_post_trans	5.200s	217.766us	0	1	0.00
	lc_ctrl_jtag_prog_failure	3.690s	1249.243us	1	1	100.00
	lc_ctrl_jtag_errors	52.420s	3057.986us	1	1	100.00
	lc_ctrl_jtag_access	13.010s	1583.601us	1	1	100.00
	lc_ctrl_jtag_regwen_during_op	16.270s	3151.545us	1	1	100.00
jtag_priority				1	1	100.00
	lc_ctrl_jtag_priority	2.150s	758.191us	1	1	100.00
lc_ctrl_volatile_unlock				1	1	100.00
	lc_ctrl_volatile_unlock_smoke	0.960s	15.308us	1	1	100.00
stress_all				0	1	0.00
	lc_ctrl_stress_all	12.450s	4372.860us	0	1	0.00
alert_test				1	1	100.00
	lc_ctrl_alert_test	1.070s	18.466us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	lc_ctrl_tl_errors	1.310s	104.002us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	lc_ctrl_tl_errors	1.310s	104.002us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	lc_ctrl_csr_hw_reset	0.980s	54.707us	1	1	100.00
	lc_ctrl_csr_rw	0.900s	123.574us	1	1	100.00
	lc_ctrl_csr_aliasing	0.810s	82.597us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.000s	22.412us	1	1	100.00
tl_d_partial_access				4	4	100.00
	lc_ctrl_csr_hw_reset	0.980s	54.707us	1	1	100.00
	lc_ctrl_csr_rw	0.900s	123.574us	1	1	100.00
	lc_ctrl_csr_aliasing	0.810s	82.597us	1	1	100.00
	lc_ctrl_same_csr_outstanding	1.000s	22.412us	1	1	100.00

V2S

18/28 passed

64.29 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	lc_ctrl_tl_intg_err	1.970s	66.661us	1	1	100.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	lc_ctrl_tl_intg_err	1.970s	66.661us	1	1	100.00
sec_cm_transition_config_regwen				1	1	100.00
	lc_ctrl_regwen_during_op	14.700s	342.096us	1	1	100.00
sec_cm_manuf_state_sparse				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_transition_ctr_sparse				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_manuf_state_bkgn_chk				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_transition_ctr_bkgn_chk				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_state_config_sparse				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_main_fsm_sparse				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_kmac_fsm_sparse				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_main_fsm_local_esc				1	2	50.00
	lc_ctrl_state_failure	1.190s	6.920us	0	1	0.00
	lc_ctrl_sec_cm	6.000s	364.192us	1	1	100.00
sec_cm_main_fsm_global_esc				1	1	100.00
	lc_ctrl_security_escalation	4.780s	1321.806us	1	1	100.00
sec_cm_main_ctrl_flow_consistency				0	2	0.00
	lc_ctrl_state_post_trans	1.480s	47.363us	0	1	0.00
	lc_ctrl_jtag_state_post_trans	5.200s	217.766us	0	1	0.00
sec_cm_intersig_mubi				1	1	100.00
	lc_ctrl_sec_mubi	6.630s	288.699us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	lc_ctrl_sec_mubi	6.630s	288.699us	1	1	100.00
sec_cm_token_digest				1	1	100.00
	lc_ctrl_sec_token_digest	5.240s	210.337us	1	1	100.00
sec_cm_token_mux_ctrl_redun				1	1	100.00
	lc_ctrl_sec_token_mux	4.480s	1485.548us	1	1	100.00
sec_cm_token_valid_mux_redun				1	1	100.00
	lc_ctrl_sec_token_mux	4.480s	1485.548us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	lc_ctrl_stress_all_with_rand_reset	12.820s	3018.531us	0	1	0.00

Error Messages

	Test	seed	line	log context
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
	lc_ctrl_state_failure	45209735985882546813891802367515558621459052321510641889487174585365746506396	121	Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' UVM_ERROR @ 6920241 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 6920241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_state_post_trans	8667745525525274368128105594657274061840095989567977860026719654580170053124	250	Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' UVM_ERROR @ 47363138 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 47363138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	84541680934277750158838975779534966476318974731185684037558317677305702998475	1067	Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' UVM_ERROR @ 508082594 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 508082594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	10934705064016726629134979202732785482998951001675752636263154518449206687636	409	Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' UVM_ERROR @ 217765756 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 217765756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	66300202818566771432299188687488702464123253284588807982161031394567733658833	375	Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' UVM_ERROR @ 4372860263 ps: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 4372860263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	lc_ctrl_stress_all_with_rand_reset	113034101810118304622678793148651332936309061547323361072066006846709212677318	155	UVM_ERROR @ 3018530979 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses. UVM_INFO @ 3018530979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---