| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_smoke | 1 | 1 | 100.00 | |||
| mbx_smoke | 55.000s | 11689.123us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| mbx_csr_hw_reset | 4.000s | 20.933us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| mbx_csr_rw | 3.000s | 21.436us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| mbx_csr_bit_bash | 3.000s | 267.483us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| mbx_csr_aliasing | 2.000s | 31.465us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| mbx_csr_mem_rw_with_rand_reset | 2.000s | 48.785us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| mbx_csr_rw | 3.000s | 21.436us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 31.465us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| mbx_stress | 1 | 1 | 100.00 | |||
| mbx_stress | 98.000s | 10309.821us | 1 | 1 | 100.00 | |
| mbx_max_activity | 1 | 1 | 100.00 | |||
| mbx_stress_zero_delays | 115.000s | 6386.260us | 1 | 1 | 100.00 | |
| mbx_imbx_oob | 1 | 1 | 100.00 | |||
| mbx_imbx_oob | 38.000s | 3328.659us | 1 | 1 | 100.00 | |
| mbx_doe_intr_msg | 1 | 1 | 100.00 | |||
| mbx_doe_intr_msg | 24.000s | 2233.040us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| mbx_alert_test | 6.000s | 28.529us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| mbx_intr_test | 4.000s | 60.696us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 6.000s | 126.785us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| mbx_tl_errors | 6.000s | 126.785us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 4.000s | 20.933us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 3.000s | 21.436us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 31.465us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 34.523us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| mbx_csr_hw_reset | 4.000s | 20.933us | 1 | 1 | 100.00 | |
| mbx_csr_rw | 3.000s | 21.436us | 1 | 1 | 100.00 | |
| mbx_csr_aliasing | 2.000s | 31.465us | 1 | 1 | 100.00 | |
| mbx_same_csr_outstanding | 2.000s | 34.523us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| mbx_sec_cm | 6.000s | 37.887us | 1 | 1 | 100.00 | |
| mbx_tl_intg_err | 6.000s | 309.999us | 1 | 1 | 100.00 | |
| Test | seed | line | log context |
|---|