Simulation Results: otbn

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.96 %
  • code
  • 94.10 %
  • assert
  • 86.89 %
  • func
  • 91.88 %
  • block
  • 99.45 %
  • line
  • 99.56 %
  • branch
  • 93.52 %
  • toggle
  • 88.45 %
  • FSM
  • 94.87 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.81%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 82.427us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 3.000s 48.231us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 130.243us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 402.891us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 30.329us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 5.000s 39.663us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 130.243us 1 1 100.00
otbn_csr_aliasing 4.000s 30.329us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 21.000s 359.944us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 10.000s 761.766us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 25.000s 103.111us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 59.000s 273.634us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 73.000s 936.941us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 30.000s 297.793us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 8.000s 38.406us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 26.299us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 57.105us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 4.000s 14.717us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 15.166us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 245.591us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 245.591us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 3.000s 48.231us 1 1 100.00
otbn_csr_rw 3.000s 130.243us 1 1 100.00
otbn_csr_aliasing 4.000s 30.329us 1 1 100.00
otbn_same_csr_outstanding 3.000s 22.164us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 3.000s 48.231us 1 1 100.00
otbn_csr_rw 3.000s 130.243us 1 1 100.00
otbn_csr_aliasing 4.000s 30.329us 1 1 100.00
otbn_same_csr_outstanding 3.000s 22.164us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 8.000s 18.849us 1 1 100.00
otbn_dmem_err 7.000s 15.001us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 7.000s 65.935us 1 1 100.00
otbn_controller_ispr_rdata_err 7.000s 67.401us 1 1 100.00
otbn_mac_bignum_acc_err 7.000s 333.102us 1 1 100.00
otbn_urnd_err 4.000s 9.831us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 4.000s 41.682us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 6.000s 21.859us 1 1 100.00
otbn_non_sec_partial_wipe 0 1 0.00
otbn_partial_wipe 4.000s 6.150us 0 1 0.00
tl_intg_err 1 2 50.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
otbn_tl_intg_err 8.000s 118.658us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 13.000s 175.564us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 82.427us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 7.000s 15.001us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 8.000s 18.849us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 8.000s 118.658us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 38.406us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 18.849us 1 1 100.00
otbn_dmem_err 7.000s 15.001us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 26.299us 1 1 100.00
otbn_illegal_mem_acc 4.000s 41.682us 1 1 100.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 18.849us 1 1 100.00
otbn_dmem_err 7.000s 15.001us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 26.299us 1 1 100.00
otbn_illegal_mem_acc 4.000s 41.682us 1 1 100.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 8.000s 38.406us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 8.000s 18.849us 1 1 100.00
otbn_dmem_err 7.000s 15.001us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 26.299us 1 1 100.00
otbn_illegal_mem_acc 4.000s 41.682us 1 1 100.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 22.307us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 13.028us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 24.000s 83.948us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 24.000s 83.948us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 58.903us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 5.000s 203.616us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 41.818us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 41.818us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 4.000s 22.907us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 73.000s 936.941us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 6.000s 46.519us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 24.490us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 5.000s 63.328us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 107.000s 1160.606us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 100741585720906493474616123475114742129510410431778348666061498279060800112918 263
UVM_ERROR @ 1160605775 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1160605775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed
otbn_partial_wipe 115557549563299501966276409607656280503379688970750969337056203319031178900200 107
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 6150219 PS) Assertion tb.MatchingStatus_A has failed
UVM_ERROR @ 6150219 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 6150219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1386): Assertion ErrBitsKnown_A has failed
otbn_sec_cm 73214925286381976045737611386154058295881474998501372779136739165370750497738 97
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1386): (time 63328219 PS) Assertion tb.dut.ErrBitsKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,948): (time 63328219 PS) Assertion tb.dut.u_otbn_core.DoneOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,949): (time 63328219 PS) Assertion tb.dut.u_otbn_core.ImemReqOKnown_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,950): (time 63328219 PS) Assertion tb.dut.u_otbn_core.ImemAddrOKnown_AKnownEnable has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 63328219 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed