Simulation Results: otp_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 72.65 %
  • code
  • 71.78 %
  • assert
  • 93.20 %
  • func
  • 52.97 %
  • line
  • 87.35 %
  • branch
  • 83.99 %
  • cond
  • 85.68 %
  • toggle
  • 65.53 %
  • FSM
  • 36.37 %
Validation stages
V1
100.00%
V2
80.00%
V2S
98.21%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.830s 844.168us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 3.110s 1965.162us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.880s 702.225us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.170s 233.398us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.610s 497.333us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.230s 303.332us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.880s 702.225us 1 1 100.00
otp_ctrl_csr_aliasing 5.610s 497.333us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.540s 541.406us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.410s 83.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 129.530s 81208.739us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.150s 138.185us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 10.840s 1045.774us 0 1 0.00
otp_ctrl_check_fail 4.120s 368.050us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.590s 276.733us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
interface_key_check 0 1 0.00
otp_ctrl_parallel_key_req 14.850s 633.380us 0 1 0.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 4.500s 154.395us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 23.160s 555.925us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 52.730s 28346.093us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 8.550s 678.421us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 97.480s 50135.420us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.680s 149.711us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 4.180s 927.490us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.630s 527.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.630s 527.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.110s 1965.162us 1 1 100.00
otp_ctrl_csr_rw 1.880s 702.225us 1 1 100.00
otp_ctrl_csr_aliasing 5.610s 497.333us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.330s 97.160us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 3.110s 1965.162us 1 1 100.00
otp_ctrl_csr_rw 1.880s 702.225us 1 1 100.00
otp_ctrl_csr_aliasing 5.610s 497.333us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.330s 97.160us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_tl_intg_err 12.050s 1545.465us 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.050s 1545.465us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_macro_errs 52.730s 28346.093us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_macro_errs 52.730s 28346.093us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.260s 136.931us 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.150s 138.185us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 4.120s 368.050us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.360s 1405.575us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 286.810s 20027.685us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.590s 276.733us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.190s 146.020us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 52.730s 28346.093us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 89.180s 46317.554us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 20.690s 1678.294us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_partition_walk 15360465259150435148259557466786147209717449906367488419433761505373485347334 120734
UVM_ERROR @ 81208739390 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_partition_walk_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 16080 [0x3ed0]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 81208739390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch
otp_ctrl_low_freq_read 3090917872725191179090936138274354007396210585290397642591300668418982970450 86
UVM_ERROR @ 46317553652 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 46317553652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 19684831310375096349836541802471196366939798594899053849495241803861270450967 9605
UVM_ERROR @ 50135420068 ps: (otp_ctrl_base_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (16080 [0x3ed0] vs 3032406676 [0xb4beda94]) dai addr 3ed0 rdata0 readout mismatch
UVM_INFO @ 50135420068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_*
otp_ctrl_background_chks 56273334745914116430112682007362834910756465203151255877717197628237589458281 7271
UVM_ERROR @ 1045773611 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (4 [0x4] vs 5 [0x5]) reg name: otp_ctrl_core_reg_block.err_code_22
UVM_INFO @ 1045773611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1320) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 36647639225945547377730537726865297505848390667031826578836250687316343334598 3993
UVM_ERROR @ 368049625 ps: (otp_ctrl_scoreboard.sv:1320) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 16384 [0x4000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 368049625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:671) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr
otp_ctrl_parallel_key_req 109211779347002175095905388684948228731893018023123511586450779925382693576756 20953
UVM_ERROR @ 633379613 ps: (otp_ctrl_scoreboard.sv:671) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x0 [0] vs 0x1 [1]) Interrupt_pin: OtpErr
UVM_INFO @ 633379613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:605) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 88363118763193978122914593404426535772545613154675273707345351950661745138092 248
UVM_ERROR @ 1678294421 ps: (cip_base_scoreboard.sv:605) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 1678294421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---