Simulation Results: rom_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.56 %
  • code
  • 98.00 %
  • assert
  • 95.49 %
  • func
  • 96.18 %
  • line
  • 99.46 %
  • branch
  • 98.18 %
  • cond
  • 93.46 %
  • toggle
  • 98.88 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.320s 133.999us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.110s 166.362us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 4.160s 165.087us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.890s 1857.314us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.940s 300.545us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.050s 483.644us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 4.160s 165.087us 1 1 100.00
rom_ctrl_csr_aliasing 3.940s 300.545us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.560s 534.574us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.120s 386.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 5.090s 182.981us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 15.820s 602.793us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 6.250s 717.637us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.470s 165.940us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.390s 235.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.390s 235.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.110s 166.362us 1 1 100.00
rom_ctrl_csr_rw 4.160s 165.087us 1 1 100.00
rom_ctrl_csr_aliasing 3.940s 300.545us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.260s 208.056us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 5.110s 166.362us 1 1 100.00
rom_ctrl_csr_rw 4.160s 165.087us 1 1 100.00
rom_ctrl_csr_aliasing 3.940s 300.545us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.260s 208.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.630s 583.310us 1 1 100.00
tl_intg_err 1 2 50.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
rom_ctrl_tl_intg_err 41.900s 1878.084us 1 1 100.00
prim_fsm_check 0 1 0.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
prim_count_check 0 1 0.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_compare_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.320s 133.999us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.320s 133.999us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.320s 133.999us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 41.900s 1878.084us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
rom_ctrl_kmac_err_chk 6.250s 717.637us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 46.230s 1380.719us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.630s 583.310us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
rom_ctrl_sec_cm 98.000s 585.539us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 44.720s 14345.162us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
rom_ctrl_sec_cm 40262921558497222348777328880900204094830281610536594612778685471261375249206 240
Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26390895ps failed at 26390895ps
Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
"src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26390895ps failed at 26390895ps
Offending '(curr_fwd | pend_req[d2h.d_source].pend)'