Simulation Results: rom_ctrl

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.58 %
  • code
  • 98.96 %
  • assert
  • 96.65 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 98.54 %
  • cond
  • 96.88 %
  • toggle
  • 99.92 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.420s 795.951us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.100s 293.461us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 10.470s 1037.942us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.730s 4145.003us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.550s 295.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.390s 4029.835us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 10.470s 1037.942us 1 1 100.00
rom_ctrl_csr_aliasing 7.550s 295.625us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 538.869us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.100s 1162.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 6.470s 1365.372us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 28.870s 848.065us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.370s 388.811us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.110s 315.152us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 9.970s 1215.023us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 9.970s 1215.023us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.100s 293.461us 1 1 100.00
rom_ctrl_csr_rw 10.470s 1037.942us 1 1 100.00
rom_ctrl_csr_aliasing 7.550s 295.625us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.960s 1067.144us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.100s 293.461us 1 1 100.00
rom_ctrl_csr_rw 10.470s 1037.942us 1 1 100.00
rom_ctrl_csr_aliasing 7.550s 295.625us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.960s 1067.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.960s 1112.698us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
rom_ctrl_tl_intg_err 54.780s 615.710us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.420s 795.951us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.420s 795.951us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.420s 795.951us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 54.780s 615.710us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
rom_ctrl_kmac_err_chk 13.370s 388.811us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.040s 32432.496us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.960s 1112.698us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.780s 1731.167us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 111.440s 1783.486us 1 1 100.00

Error Messages

   Test seed line log context