Simulation Results: rstmgr

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.10 %
  • code
  • 99.27 %
  • assert
  • 97.44 %
  • func
  • 97.59 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.64 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.020s 61.798us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.950s 64.151us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.210s 106.160us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.110s 51.672us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.010s 66.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00
rstmgr_csr_aliasing 1.110s 51.672us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 1.390s 208.814us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 0.930s 37.846us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.950s 77.894us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.140s 793.877us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.140s 793.877us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.140s 793.877us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.140s 793.877us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 22.120s 3620.776us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.840s 42.272us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.480s 57.234us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.480s 57.234us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 64.151us 1 1 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00
rstmgr_csr_aliasing 1.110s 51.672us 1 1 100.00
rstmgr_same_csr_outstanding 0.900s 42.429us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.950s 64.151us 1 1 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00
rstmgr_csr_aliasing 1.110s 51.672us 1 1 100.00
rstmgr_same_csr_outstanding 0.900s 42.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 28.930s 6826.178us 1 1 100.00
rstmgr_tl_intg_err 2.290s 329.170us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 28.930s 6826.178us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 28.930s 6826.178us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.290s 329.170us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.990s 63.376us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 3.430s 457.401us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.800s 292.997us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 28.930s 6826.178us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.780s 36.089us 1 1 100.00

Error Messages

   Test seed line log context