Simulation Results: rv_timer

 
17/12/2025 16:09:12 sha: e57c4e9 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.27 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 95.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.660s 85.924us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.590s 19.563us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 23.165us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.870s 195.590us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.750s 40.083us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.660s 20.186us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 23.165us 1 1 100.00
rv_timer_csr_aliasing 0.750s 40.083us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.610s 86.893us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.190s 2869.154us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 141.190s 124199.282us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 141.190s 124199.282us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.050s 2613.311us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.540s 14.058us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 18.878us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.550s 199.481us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.550s 199.481us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 19.563us 1 1 100.00
rv_timer_csr_rw 0.560s 23.165us 1 1 100.00
rv_timer_csr_aliasing 0.750s 40.083us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 171.971us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.590s 19.563us 1 1 100.00
rv_timer_csr_rw 0.560s 23.165us 1 1 100.00
rv_timer_csr_aliasing 0.750s 40.083us 1 1 100.00
rv_timer_same_csr_outstanding 0.640s 171.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.820s 61.199us 1 1 100.00
rv_timer_tl_intg_err 0.930s 189.629us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.930s 189.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.520s 12.702us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.620s 216.227us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.170s 5949.180us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 81198659999115985816622671430962863220887479011748059825442480129636825526879 72
UVM_ERROR @ 216226734 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 216226734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 111150207683150840616029089358391483517258674107677518301952544508115558203039 72
UVM_FATAL @ 86893106 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf5190d04) == 0x1
UVM_INFO @ 86893106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---